Specifications

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VDD
Transistor Q1
VOB
E0
DATA
ADDRESS
ROM
µPD3055GF002-2BA
CPU
VCC
(Pin35)
µPD65005G-452-22
" L "
VDD
R4
(Pin1)
(Pin3)
(Pin2)
(Pin30)
VOT
VIN
"H"
"H"
V2ON
INT1
CPU
PDB
µPD3055GF002-2BA
POWER SUPPLY CHIP
SC371015FU
µPD65005G-452-22
GATE ARRAY
(Pin45)
(Pin69)
(Pin29)
(Pin30)
(Pin31)
LCD drive voltages
VREG,V1~V4
When the system is start up, CPU will send "H" signal to VIN terminal of gate array from V2ON
terminal. Then, gate array will send "H" signal from VOT terminal to release interruption signal
INT1 of CPU and also, it will be sent to PDB terminal of power supply chip to generate LCD drive
voltages.
After gate array send VOT signal, gate array send "L" signal from VOB terminal to base terminal of
transistor Q1. Then, the VDD is applied to ROM (operation program), CPU can read a ROM
program data by E0 signal.
4) Power supply for LCD
5) ROM driving transistor
GATE ARRAY
µPD23C2001
EGW342