Specifications

— 19 —
Pin No. Name In/Out Status Status Description
of OFF of ON
2~12,23, A0~A17 In L Pulse Address bus line (A0~A14, RA15~RA17)
25~30
13~15, 17~21 O0~O7 Out L Pulse Data bus line (IO0~IO7)
16 GND In L L GND terminal
22 CE In H Pulse Chip enable signal from Gate array
24 OE In L Pulse Output enable signal from Gate array
31 PGM In L Pulse Address line (RA18)
1, 32 VPP, VCC In L H VDD terminal
9-5. Operation program ROM pin descriptions
Pin No. Name In/Out Status Status Description
of OFF of ON
1~10,21, A0~A14 In L Pulse Address bus line (A0~A14)
23~26
11~13, 15~19 IO0~IO7 Out L Pulse Data bus line (IO0~IO7)
14 GND In L L GND terminal
20 CS In H Pulse Chip enable signal from Gate array
22 OE In L Pulse Output enable signal from Gate array
28 VCC In L H VDD terminal
27 WE In H Pulse Write enable signal from CPU
9-6. RAM pin descriptions (µPD43256G)
Pin No. Name In/Out Description
57 MS2 Out Not used
58 OEO Out Output enable for ROM
59 BZ1 Out Buzzer signal
60 OTP In Connected to GND
61 BZ2 Out Buzzer signal
62 SWO Out Main switch control signal
63 VH4(VCC) In 9V input
64 TXO Out Transmission data output terminal