Specifications

— 16 —
VDD
VOB
DATA
ADDRESS
HD62076C03
CPU
VCC
" L "
VDD
R11
(Pin1)
(Pin3)
(Pin2)
After gate array gets V20N signal from CPU, gate array sends "L" signal from VOB terminal to base
terminal of transistor Q3. Then, the VDD is applied to ROM (operation program), CPU can read a ROM
program data.
8) ROM driving transistor
GATE ARRAY
OE
(Pin58) (Pin24)
Transistor Q3
2SA1411
(Pin28)
(Pin32)
OEO
MSO
ROM
µPD23C2001
EGW-344
CE
"Pulse"
SSC2571F0A
"Pulse"
(Pin53)
(Pin22)
VIN
V20N
from CPU
(Pin24)