Specifications

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A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
IO0
IO1
IO2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CS
IO7
IO6
IO5
IO4
IO3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
A13
A8
A9
A11
A10
IO7
IO6
IO5
IO4
IO3
IO0
IO1
IO2
VSS
DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS BUS
CXK58257AM
0.1µ
Pin No. Name In/Out Status Status Description
of OFF of ON
2~12,23, A0~A18 In L Pulse Address bus line (A0~A14, RA15~RA18)
25~31
13~15, 17~21 O0~O7 Out L Pulse Data bus line (IO0~IO7)
16 GND In L L GND terminal
22 CE In H Pulse Chip enable signal from CPU (CS ROM)
24 OE In L Pulse Output enable signal / GND
1, 32 VPP, VCC In L H VDD terminal
Pin No. Signal I/O Function
64,65 OSC I/O I/O Clock terminal (DT-26S)
67,69~71 V1 ~ 4 Voltage for LCD driver
OFF: 0[V] ON: V1: 0.64(Light) ~ 1.29(Dark)[V]
V2: 1.29 ~ 2.56 [V]
V3: 3.99 ~ 2.71 [V]
V4: 4.64 ~ 3.99 [V]
68 NC - Not used
72 INTO In Low battery detection INTO<5.2[V]=> No power on
73 STNT - Switch terminal for LCD construction
74 VLCD In Power supply/5.3[V]
75 ~ 171 S0 ~ 95 Out Segment signal for display
172 ~ 199 C5 ~ 32 Out Common signal for display
168,200 NC - Not used
6-3. OPERATION PROGRAM ROM PIN DESCRIPTIONS (µPD23C1001)
6-2. RAM: CXK58257AM (LSI2, LSI3)
CPU (CSRA1 or 2)
CPU (WEB)
A0 ~ A14 : Address input signal
IO0 ~ IO7 : Data signal (Input/Output)
WE : Write enable signal
CS : Chip select signal
OE : Output enable signal