Specifications

CONSTRUCTION
Fig. 2: Effective biasing of PNP transistors using set 1 binary numbers
Fig. 3: Effective biasing of NPN transistors using set 2 binary numbers
the base in different terminals (1, 2, or 3)
on the socket, until the desired results are
obtained. To alert the user about this ac-
tion, a message ‘Adjust
LED ’ blinks on the
display (refer error processing routine in
the software program).
The circuit
The binary number generator. In this
section,
IC 1 (an NE 555 timer) is used as a
clock pulse generator, oscillating at about
45 Hz. The output of
IC 1 is applied to clock
pin 14 of
IC 2 (4017-decade counter). As a
result, the counter advances sequentially
from decimal 0 to 3, raising outputs
Q 0, Q 1,
and Q 2 to logic-1 level. On reaching the
next count, pin 7 (output
Q 3) goes high and
it resets the counter. So, the three outputs
( Q 0, Q 1, and Q 2) jointly produce three binary
numbers, continuously, in a sequential
manner (see Table II).
Q 0 through Q 2 outputs of IC 2 are con-
nected to in-
puts of
IC 3
(7486, quad 2-
input
EX - OR
gate). Gates
of
IC 3 are so
wired that
they function
as controlled
EX - OR gates.
The outputs
of
IC 3 are
controlled by
the logic level
at pin 12.
Thus, we ob-
tain two sets
of outputs
(marked
Q 0,
Q 1, and Q 2)
from
IC 3 as
given in
Tables III
(for pin 12 at
logic 1) and
IV (for pin 12
at logic 0) re-
spectively.
One of
these two
sets would be
chosen for
the output by
the software,
by control-
ling the logi-
cal state of
pin 12. Set-1 is used to identify the base
and type (npn or pnp) of the ‘transistor
under test,’ whereas set-2 is exclusively
used for identification of the collector lead,
if the device is of npn type.
The interface. The three data out-
put lines, carrying the stated binary num-
bers (coming from pins 3, 6, and 8 of
IC 3),
are connected separately to three bi-di-
rectional analogue switches
SW 1, SW 2, and
SW 3 inside IC 5 ( CD 4066). The other sides of
the switches are connected to the termi-
nals of the test socket through some other
components shown in Fig. 1. The control
line of
IC3 (pin 12) is connected to the
analogue switch
SW4 via pin 3 of IC5. The
other side of
SW4 (pin 4) is grounded. If
switch
SW4 is closed by the software,
set-1 binary numbers are applied to the
device under test, and when it is open,
set-2 binary numbers are applied.
To clearly understand the function-
ing of the circuit, let us assume that the
‘transistor under test’ is inserted with its
collector in slot-3, the base in slot-2, and
the emitter in slot-1 of the testing socket.
Initially, during identification of the
base and type of the device, all the ana-
logue switches, except
SW 4, are closed by
the software, applying set-1 binary num-
bers to the device. Now, if the device is of
pnp type, each time the binary number
100 is generated at the output of
IC 3, the
BC junction is forward-biased, and hence,
a conventional current flows through the
junction as follows:
Q 2 (logic 1) à SW 3 à R 9 à internal LED of
IC 4 à slot3 à collector lead à CB junction
à base lead à slot-2 à D3 à pin 10 of
IC 5 à SW 2 à Q 1 (logic 0).
Similarly, when the binary number
001
is generated, another current would flow
through the
BE junction and the internal
LED of IC 7. The number 010 has no effect,
as in this case both the
BC and BE junc-
tions become reversed biased.
From the above discussion it is ap-
parent that in the present situation, as
the internal
LED S of IC 4 and that of IC 7 are
forward-biased, they would go on produc-
ing pulsating optical signals, which would
be converted into electrical voltages by
the respective internal photo-transistors.
The amplified pulsating
DC voltages are
available across their emitter resistors
R7
and R17 respectively. The emitter follow-
ers configured around transistors
T1 and
T3 raise the power level of the opto-
coupler’s output, while capacitors
C3 and
C5 minimise the ripple levels in the out-
puts of emitter followers.
During initialisation,
8155 is configured
with port
A as an input and ports B and C
as output by sending control word 0E(H)
to its control register.
Taking output of transistor
T1 as
MSB(D2), and that of T3 as LSB(D0), the data
that is formed during the base identifica-
tion, is
101 (binary). The microprocessor
under the software control, receives this
data through port
A of 8155 PPI (port num-
ber 81). Since all the bits of the higher
nibble are masked by the software, the
data become
0000 0101=05(H). This data is
stored at location
216 A in memory and
termed in the software as base-Id.
Now, if the device is of npn type, the
only binary number that would be effec-
tive is
010. Under the influence of this
number both
BC and BE junctions would
be forward-biased simultaneously, and
hence conventional current would flow in
the following two paths:
8