Specifications

CONSTRUCTION
74
reset pin 4.
During the low-level period of gate
N3, output of gate N4 is ‘high’ and the
flip-flop (IC4) is in the reset state. If
any one of the ten switches is pressed,
even though clock pulses are present at
clock input (pin 3) of IC4, the Q output
will not change, as this IC is in the reset
state.
When the output of gate N3 is ‘high’,
the output of gate N4 is ‘low’, which clears
IC4 from the reset state. If the player
presses the correct switch, a clock pulse
is applied to the clock input (pin 3) of IC
CD4027. The ‘high’ level data from J in-
put is transferred to Q output (pin 1) of
this IC and IC5 advances by one count,
which means ten points (DIS.2 is always
zero). Now Q output (pin 2) of IC4, which
is connected to J input, goes ‘low’. As both
J and K inputs are at low level, IC4 is
inhibited and further clock pulses to pin
3 of IC4 have no effect.
Score counter and scoreboard.
This block comprises two decade counter/
decoder/7-segment display driver ICs
CD4033 (IC5, IC6), and three common
cathode 7-segment LED displays (DIS.2
through DIS.4). The ‘a’ through ‘f’
segments of DIS.1, meant for units,
are directly connected to positive supply
rail and its cathode is connected to nega-
tive supply rail through a 1k (R12) cur-
rent-limiting resistor. Thus it always
shows zero.
The Q output (pin 1) of IC4 is con-
nected to clock input (pin 1) of IC5, the
tens counter. The carry-out (pin 5) of IC5
is connected to the clock input (pin 1) of
IC6 for cascading hundreds counter. The
CE (pin 2) and Lamp Test (pin 14) of both
IC5 and IC6 are grounded, for proper
functioning. Both resets (pin 15) are
grounded through a 100k (R9) resistor and
connected to positive supply, through re-
set switch S10.
Ripple blanking input (pin 3) of IC6
is grounded, so the leading zero to be dis-
played in DIS.4 will be blanked out. The
ripple blanking output (pin 4) will be low
while the number to be displayed is zero.
Likewise, zero will be blanked out in dis-
play DIS.3, because RB0 of IC6 is con-
nected to RB1 of IC5. So when reset
switch S10 is depressed, the unit counter
display shows only zero and the other two
displays are blanked out.
The maximum score which can be dis-
played is 1000, after which it automati-
cally resets to zero.
Sound-effect generator. For simplic-
ity and compactness, a piezo buzzer (con-
tinuous type) is employed. When the Q
output of IC4 goes high, after the correct
switch is pressed, it forward biases tran-
sistor BC547B (T2) and drives the piezo
buzzer. This produces a beep sound for
confirmation of successful shooting of that
number.
Construction
This circuit can be assembled on a
readymade PCB or strip board. However,
a proper single-sided PCB for the circuit
of Fig. 2 is shown in Fig. 3 and its compo-
nent layout is shown in Fig. 4. For
switches, push-to-on tactile or membrane
switches can be used. For power supply,
four pen-torch cells (AA3) can be used with
a battery holder. DC IN socket is provided
for connecting a battery eliminator for op-
erating it on mains supply.

1. The spurious pulses must be ig-
nored.
2. The counter must advance only on
the first pressing of the switch for a num-
ber and further pressing must be ignored.
3. The pressing of the switch should
be effected only after the corresponding
number is displayed.
To fulfil all these conditions, the
dual JK flip-flop IC CD4027 (IC4) is
employed and only one of the two flip-
flops is used. The flip-flop is inhibited
when both J and K inputs are low
(requirements 1 and 2). The data on
the J input is transferred to the Q output
for a positive-going clock pulse only
(requirement 3). The K input (pin 5) of
IC CD4027 is grounded and J input
(pin 6) is connected to Q output (pin 2).
One terminal of all the ten switches is
connected to clock input (pin 3) of IC4.
Control pulses from gate N3 (pin 10)
are inverted by gate N4 before it goes to
Fig. 3: Actual-size, single-sided PCB layout
Fig. 4: Component layout for the PCB