Specifications

CONSTRUCTION
goes from ‘low’ to
‘high’, it acts as
a clock (CLK1)
for first section
of IC3. As a re-
sult Q1 of the
IC3 goes ‘low’ to
trigger IC4,
which produces
a pulse of about
3.5-second dura-
tion at its output
pin 3. The out-
put of IC4 is in-
verted by tran-
sistor T1, which
toggles the sec-
ond JK flip-flop
inside IC3. As a
consequence, its
Q2 output goes
‘low’ and the
count present at
the parallel load
inputs are
loaded. The par-
allel count
loaded depends
on the number of
clock pulses ar-
riving at IC5
within these 3.5-
seconds, which
again depends
on the number of
claps produced
within the same
period. Table I
shows the status
at parallel in-
puts of IC5 and
the status of re-
lay RL1 or the
device connected
via the normally-
open contacts of
the relay to the
supply.
The first clap
activates the
monostable flip-
flop IC4. It is
clear from Table
I that if no fur-
ther claps occur
within 3.5 sec-
onds of the first
clap, the parallel
inputs to IC5 be-
come 0000 be-
Fig. 1: Schematic diagram of smart clap switch
57