Specifications

182
CONSTRUCTION
nected externally between pins 18 and 19.
The crystal frequency should range be-
tween 1 MHz and 16 MHz for proper func-
tioning of the controller. If this frequency
is taken below 1 MHz, there is a chance
of losing data of its internal RAM.
Pin 31 happens to
be the external access
pin for the controller.
If this particular pin
is grounded, 8051
fetches program from
the externally con-
nected ROM/EPROM.
And if it is connected
to Vcc, it starts execut-
ing the program from
the internal ROM that
has 4k address space
(0000H-0FFFH). For
8031, there is no inter-
nal ROM present, and
hence this pin has to
be grounded for its
proper operation.
When internal
ROM is used, and if the
program exceeds the 4k
internal ROM address
space, then after the
last address 0FFFH, it
starts executing the
program from exter-
nally connected ROM/
EPROM. The exter-
nally connected ROM/
EPROM can be in-
creased up to 64k, i.e.
0000H-FFFFH. In the
case of RAM, the same
can be extended up to
64k.
It should be noted
that the 8051 is
organised such that
data memory and pro-
gram memory can be
two entirely different
physical memory enti-
ties. Another impor-
tant aspect to be dis-
cussed relates to its input-out-
put (I/O) ports. The 8051 has
a total of four 8-bit ports,
namely, P0, P1, P2, and P3.
P0. The P0 port may be
used as input, output, or as
combined low-order address
and a bidirectional data bus
for external memory, which is
an alternate function.
P1. Port P1 does not have any alter-
nate function. It means that these pins
are used for interfacing input-output de-
vices like ADC, DAC, 7-segment displays,
LCD, keyboard, etc.
P2. Port P2 happens to be the high-
order address lines, i.e. A8-A15. This port
can be used for interfacing I/O devices. It
should be noted that port 2 is changed
momentarily by the address signals when
supplying the byte of a 16-bit address.
P3. Port 3 functions in a fashion simi-
lar to that of port 1. Each pin of port P3
performs different operations as shown
in Table I.
Hardware
The controller is interfaced with the
external memory (EPROM) via the oc-
Fig. 2: PCB layout for the circuit
Fig. 3: Component layout for the PCB
TABLE I
Pins Use
P3.0 (RXD) Receive data serially
P3.1 (TXD) Transmit data serially
P3.2 (INT0) External interrupt zero
P3.3 (INT1) External interrupt one
P3.4 (T0) I/P pin for timer 0
P3.5 (T1) I/P pin for timer1
P3.6 (WR) External memory write pulse
P3.7 (RD) External memory read pulse