Specifications

sion of switch S1 up to the count 101.
When switch S1 is depressed once again,
normally the counter should read 110. But
the two most significant bits of the counter
force the output of NAND gate (IC7) to
go low to reset the counter to 000. The
counter now begins to count through its
normal sequence all over again, upon ev-
ery key depression.
The circuit does not provide the facil-
ity to memorise its previous setting once
it is powered off or when there is a mains
failure.
counter upon every depression of switch
S1. Upon the arrival of first clock edge, the
counter advances to 001. The outputs of
the counter go to IC4 (IC 74138), which is
a 3-line to 8-line decoder. When IC4 re-
ceives the input address 001, its output Q1
goes low, while other outputs Q0 and Q2
through Q7 stay high. The output Q1, af-
ter inversion, drives transistor T1, which
actuates relay RL1. Now power is deliv-
ered to the fan through the N/O contact
RL1/1 of relay RL1 and the tapped resistor
R
T
. For the tapped resistor R
T
, one can use
the resistance found in conventional fan
regulators with rotary speed regulation.
The outputs of the counter also go to
IC6 (IC 7447), a BCD to 7-segment code
converter, which, in turn, drives a 7-seg-
ment LED display. When switch S1 is de-
pressed once again, the counter advances
to count 010. Now, the output Q2 of IC4
goes low, while Q0, Q1 and Q3 through
Q7 go high or remain high. This forces
transistor T2 to saturation and actuates
relay RL2. The display indicates the
counter output in a 7-segment fashion.
The counter proceeds through its nor-
mal count sequence upon every depres-
www.electronicsforu.com
a portal dedicated to electronics enthusiasts
172