Specifications

CONSTRUCTION
7473, which pro-
duces the two
50Hz square-
wave outputs at
its pins 8 and 9
with a phase dif-
ference of 180
degrees between
the two. One of
the outputs is
coupled to the
base of transis-
tor T1 through
diode D1 and se-
ries current-lim-
iting resistor R3,
while the second
output is given
to the base of
transistor T2
through diode
D2 and series
resistor R4.
Transistors T1
and T2 act as
MOSEFT driv-
ers.
Power out-
put stage. The
collector of tran-
sistor T1 is con-
nected to the
gates of
MOSFETs M1
through M3 (re-
ferred to as
bank 1), while
that of transis-
tor T2 is con-
nected to the
gates of
MOSFETs M4
through M6
(referred to
as bank 2).
MOSFETs M1
through M3 are
connected in
parallel—gates
of MOSFETs M1
through M3 and
those of
MOSFETs M4
through M6 are
made common.
Similarly, drains
and sources of
MOSFETs in
each bank are
paralleled as
Fig. 2: Schematic diagram of MOSFET-based sinewave inverter optional circuit of no-load/over-load protector (within dotted lines)
158