Specifications

CIRCUIT IDEAS
T
he logic signals to step, run, and
halt a computer or other appro-
priate digital devices or system
may be generated by this circuit, which
is operated by just a single pushbutton.
The only active devices used are a dual
one-shot and a dual flip-flop ICs.
The step command is generated each
time the pushbutton is depressed momen-
(BASED ON MOTOROLA APPLICATION NOTE)
S.C. DWIVEDI
tarily. The run command occurs if the but-
ton is held down for a time exceeding about
300 ms.
This time (300 ms) represents an ex-
cellent compromise between circuit speed
and accuracy. If this duration is made
much shorter, the
circuit may fail to
differentiate be-
tween the step and
run commands, and
may generate the
run command when
the step command is
desired, or vice
versa. Also, repeat-
edly pressing the
button rapidly to ini-
tiate step functions will generate the run
command if the duration is set for much
more than 300 ms. Finally, the device will
be halted if the pushbutton is depressed
momentarily when the circuit is in the
run mode.
As shown in the figure, module A1
acts as an effective switch debouncer for
the pushbutton. For a step command, pok-
ing the button quickly will cause ‘Q’ out-
put of A1 to go high and trigger module
A2 (the monostable for run-and-step op-
erations). The Q output of A1 is also fed to
‘D’ input of module A3 (the run-and idle
latch). At the same time, the active low Q
output of A1 triggers the step one-shot
A4, yielding the step function.
The sequence of events discussed above
also describes
the initial por-
tion of the run
command,
whereby the
step pulse can
be used to
manually ad-
vance a
computer’s
program
counter by 1.
The run pulse
can be used to
instruct the
computer to
rapidly ex-
ecute succeed-
ing steps auto-
matically. The
Q* output of
A2 moves high
300 ms after the pushbutton is depressed.
The positive going (trailing) edge of this
pulse then clocks the state of the
pushbutton (as detected by A1) into A3.
If the circuit/computer is in run mode,
then pressing of the button will cause the
circuit to halt the computer by clocking
in a logic ‘0’ (synchronously available at
data input pin) to the run-and-idle latch
A3. Note that the step pulse generated at
the start of the halt sequence, as shown
in the timing diagram, is of no conse-
quence, since when the step is received,
the machine is already in the run mode
and will override that command.
ONE BUTTON FOR STEP, RUN,
AND HALT COMMANDS
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