Specifications

148
CONSTRUCTION
data corre-
sponding to
each depres-
sion of key is
written into se-
quential loca-
tions of the se-
lected page/
pages
Operate/
verify mode.
In operate/
verify mode position of switch S1, the
state of OE2 (pin 19) of IC2, and OE*
and WE signals (at pin 20 and 21 of
RAM 6116) is reverse of that at register
mode. Thus, RAM is selected for reading
the data corresponding to the address se-
lected via counter IC8. At the same time,
IC3 (74HC688), an 8-bit comparator (con-
figured here as a 5-bit comparator), is
enabled. It will compare the entered digit
of secret code with the SRAM contents
at the location selected by counter IC8,
assuming that before the start of verifi-
cation operation, counter IC8 is reset with
the help of reset switch S3 so that first
address selected is ‘0’.
When data is entered via keypad for
verification, i.e. to open or close the lock,
address of SRAM (IC5) will be
of data into the RAM, while 8-bit com-
parator IC3 is disabled. Thus, the key-
board data (corresponding to a pressed
key) at the output of IC1, buffered by IC2,
is present at D4 through D7 pins of RAM
(IC5). This data gets stored at an address
corresponding to the selected page, via 4-
way DIP switch S2, and its location is
determined by outputs Q1 through Q5 of
12-bit counter IC8.
If the first key-press operation occurs
soon after pressing reset switch S3, the
first data gets entered at address ‘0’ of
the selected page. On release of the key,
the counter (IC8) increments by one (ad-
dress also increments by one), as a result
of clock pulse applied to its pin 10. Hence,
the next key-pressed data will get writ-
ten at the incremented address. Thus,
Fig. 2: Power supply for the code lock
Fig. 3: Actual-size, single-sided PCB for circuits shown in Figs 1 and 2
www.electronicsf
oru.com
a portal dedicated to electronics enthusiasts