Specifications

CONSTRUCTION
each) and then coupling it to the base of
transistor BC148B to invert the sync sig-
nals at its collector.
The video signal is the dot pattern
obtained from the shift register IC
74LS165. This register is loaded at each
character-clock beginning. The shifting is
accomplished by the dot clock. Pin 7 of IC
74LS165 outputs the dot pattern. This is
combined with the sync signal at the col-
lector of transistor BC148B using a diode
and a series resistor. Composite video out-
put is available for connection to the TV
monitor from the collector of transistor
BC148B.
Video RAM. The 62256 is a 32k x 8-
bit static RAM; but only 16k address space
has been used here, which makes for a
raster of 512 x 256 pixels, or 128k pixels,
or 128/8=16kB. The RAM 62256 has
A0-A13 address lines for its 16k capacity.
The MA0-MA5, the character-count out-
puts, are given to its first six address pins
A0-A5. Either the 8085 or these charac-
ter-count signals can select these low-
order video memory addresses. A set of
quad 2-line to 1-line data selector ICs 7
and 8 (74157) is used under control of
CS1 (not CS1) to switch between them.
Normally, the MA0-MA5 lines have
access so as to continuously display
the video memory contents, but when
the 8085 writes fresh data, it switches to
A0-A5.
Memory access of the video RAM is
done on the basis of a high-order address
and a low-order address. The eight high-
order address values are written into
74LS373 latch (IC21) by the 8085 using
CS2. The output enable of this latch is
under control of CS1, so that the data
previously written into this latch can be
accessed when CS1 is enabled (active low).
The latched outputs of IC21 are for se-
lecting the A6 to A13 pins of the video
memory.
By this scheme of low-order and high-
order addressing, the memory group of
16k of video RAM is conveniently accessed
by just 2k space of the 8085’s memory
area. Further, it also facilitates software
writing. The high address data is that
of the row and line-select information.
These are decided by the software based
on what row of character and which line
of that row is to be filled from the charac-
ter code EPROM, as a specific key is
depressed. The character slot information
in any row is then written by a memory
write into the low-order address of the
RAM.
By using 74LS373, the data into the
latch is written with its output in tri-state
condition (pin 1 high). When pin 1 of
74LS373 is enabled (low), the RAM chip
is written with the character slot data by
the 8085 into its low-order address. Nor-
mally, the lines RA0-RA3 and MA6-MA9
Fig. 5: Actual-size, component-side track layout for the schematic diagram of Fig. 1
137