Specifications

130
CONSTRUCTION
9380 31FF9F GOOD1:LXI SP,9FFFH
9383 211094 LXI H,9410H
9386 3E00 MVI A,00H
9388 0600 MVI B,00H
938A CD160B CALL OUTPT ; (UTILITY SUBROUTINE IN THE KIT TO
; DISPLAY ACC CONTENT)
938D 76 HLT
;DATA TABLE
;NAND ;AND ;OR ;EXOR ;NOT ;NOR
9300 24 9310 00 9320 00 9330 00 9340 2A 9360 09
9301 09 9311 00 9321 00 9331 00 9341 15 9361 26
9302 2D 9312 09 9322 2D 9332 2D 9342 15 9362 12
9303 2D 9313 24 9323 2D 9333 2D 9343 2A 9363 12
9304 36 9314 12 9324 36 9334 36 9364 24
9305 1B 9315 12 9325 1B 9335 1B ;BUFFER 9365 09
9306 1B 9316 3F 9326 3F 9336 1B 9350 00 9366 36
9307 36 9317 3F 9327 3F 9337 36 9351 00 9367 1B
9352 3F
;ICIC ;BADD ;GOOD 9353 3F
93A0 0C 9400 0D 9410 0D
93A1 01 9401 0D 9411 00
93A2 0C 9402 0A 9412 00
93A3 01 9403 0B 9413 0C
SYMBOL TABLE :
A 9212 TYPE1 925E LP1 9260 TYPE2 9275
LP2 9277 TYPE3 9290 LP3 9292 PROCESS 92B1
LP4 92C2 BAD 92E0 GOOD 92F5 BAD1 9370
GOOD1 9370
NOTE: 1. * INDICATES THAT OPCODE IS DEPENDENT ON I/O ADDRESS USED
IN THE SPECIFIC KIT
2. @ INDICATES THE ROUTINE MODIFIED BY EFY FOR DYNALOG KIT
TABLE II: LOGIC STATES OF 8255 PORTS
8255 (A) 8255 (B)
ZIF Socket Pin No. 654321 1312111098
Reg. C Ports C5 C4 C3 C2 C1 C0 HEX C5 C4 C3 C2 C1 C0 HEX
Reg. A/B Ports B2 B1 B0 A2 A1 A0 Eq. A0 A1 A2 B0 B1 B2 Eq.
OI
2
I
1
OI
2
I
1
I
1
I
2
OI
1
I
2
O
1001002400100109
1011012D1011012D
110110360110111B
0110111B11011036
0000000000000000
0010010910010024
0100101201001012
1111113F1111113F
0000000000000000
1011012D1011012D
110110360110111B
1111113F1111113F
0000000000000000
1011012D1011012D
110110360110111B
0110111B11011036
OIOIOI IOIOIO
1010102A01010115
010101151010102A
0000000000000000
1111113F1111113F
I
2
I
1
OI
2
I
1
OOI
2
I
1
OI
2
I
1
0010010910010026
0100101201001012
1001002400100109
110110360110111B
I = INPUT; O = OUTPUT; Hex Eq = Hex digits read via Reg. C
Note:- Pin 7 of ZIF socket is connected to ground and pin 14 is connected to +5V.
IC Description
NAND (7400)
(Type 1)
AND (7408)
(Type 1)
OR (7432)
(Type 1)
Ex-OR (7486)
(Type 1)
Invertor (7404)
(Type 2)
Buffer (7407)
(Type 2)
NOR (7402)
(Type 3)
Fig. 3: PCB layout for interface
Fig. 4: Component layout for PCB
ternate result-indicating subroutines spe-
cifically used at EFY lab during testing
are also included for benefit of the read-
ers. The complete details of address space
used for the program and peripheral de-
vices are given before the actual program.
The program is self-explanatory, with suit-
able comments added wherever required.
Although hardware interface circuit
can be assembled easily on a general-pur-
pose PCB, nevertheless an actual-size
single-sided PCB pattern for the same is
shown in Fig. 3 and its component layout
is given in Fig. 4.