Specifications

CONSTRUCTION
tive locations for each IC, for every com-
bination of inputs. If actual data read tal-
lies with the stored data for all combina-
tions of inputs, message ‘GOOD’ is dis-
played on the kit’s display. If any of the
result fails, i.e. if any of the gates is not
working properly, message ‘BAD’ is dis-
played on the 8085 kit.
For convenience, the ICs having iden-
tical input/output pins and requiring iden-
tical input combinations, have been
grouped under one type. (7400, 7408, 7432,
and 7486 have been grouped as ‘Type 1’,
while 7404 and 7407 have been grouped
as ‘Type 2’, and 7402 as ‘Type 3’.)
When the software program (modified
at EFY for working on Dynalog’s Micro
Friend-ILC-V2 kit) is executed on the 8085
kit, the display shows ‘ICIC’. Now enter
the last two digits of the IC number to be
tested (the last but one followed by the
last one, for instance, for IC 7404 enter 0
followed by 4). Please take care to place
the IC in the ZIF socket with proper
orientation and press ‘Next’. Depending
on performance of all the gates of ‘IC un-
der test’, the message ‘GOOD’ or ‘BAD’
will appear on its display.
For addressing peripheral devices
(8255, 8279), I/O mapped address scheme
has been employed. At EFY, the addresses
have been modified in accordance with
the Dynalog kit used for the purpose.
Other users would need to modify the pro-
gram address space as well as input-out-
put addresses for the peripherals suitably,
in accordance with the specific kit used
by them. Such opcodes which are input-
output address dependent have been an-
notated with an asterisk mark. The al-
IC Tester Program Environment
MEMORY MAP (MAY VARY FROM KIT TO KIT):
RAM LOCATIONS USED FOR PROGRAM : 9200H - 9450H
STACK POINTER INITIALISED : 9FFFH
PORTA (OUTPUT) OF A8255/B8255 : 08/10
PORTB (OUTPUT) OF A8255/B8255 : 09/11
PORTC (INPUT) OF A8255/B8255 : 0A/12
CONTROL WORD REGISTER OF A8255/B8255 : 0B/13
PROGRAM LISTING
Add. Opcode Label Mnemonics Comments
9200 31FF9F LXI SP,9FFFH
9203 21A093 LXI H,93A0H
9206 3E00 MVI A,00H
9208 0600 MVI B,00H
920A CD160B* CALL OUTPT ;(UTILITY SUBROUTINE IN THE KIT
; TO DISPLAY ACC CONTENT)
920D CD640A* CALL RDKBD ;(UTILITY SUBROUTINE IN THE KIT
; TO ACCEPT ONE HEX DIGIT FROM THE
; KEYBOARD AND STORE IN THE ACC)
9210 0E04 MVI C,04H
9212 07 A: RLC ; SHIFTED TO SECOND(TENS) PLACE
9213 0D DCR C
9214 C21292 JNZ A
9217 325094 STA 9450H
921A CD640A CALL RDKBD ; (UTILITY SUBROUTINE IN THE KIT
; TO ACCEPT ONE HEX DIGIT FROM
921D 215094 LXI H,9450H ; THE KEYBOARD AND STORE IN
; THE ACC)
9220 86 ADD M ; COMBINE TWO KEYBOARD ENTRIES
9221 47 MOV B,A
9222 210093 LXI H,9300H
9225 FE00 CPI 00H ; (NAND IC)
9227 CA5E92 JZ TYPE1
922A 211093 LXI H,9310H
922D FE08 CPI 08H ; (AND IC)
922F CA5E92 JZ TYPE1
9232 212093 LXI H,9320H
9235 FE32 CPI 32H ; (OR IC)
9237 CA5E92 JZ TYPE1
923A 213093 LXI H,9330H
923D FE86 CPI 86H ; (EXOR IC)
923F CA5E92 JZ TYPE1
9242 214093 LXI H,9340H
9245 FE04 CPI 04H ; (NOT IC)
9247 CA7592 JZ TYPE2
924A 215093 LXI H,9350H
924D FE07 CPI 07H ; (BUFFER IC)
924F CA7592 JZ TYPE2
9252 216093 LXI H,9360H
9255 FE02 CPI 02H ; (NOR IC)
9257 CA9092 JZ TYPE3
925A 76 HLT ;IN SOME 8085 KITS SUCH AS THAT FROM DYNALOG
; PROGRAM IS TERMINATED WITH ‘RST1’IN PLACE OF ‘HLT’
; NAND, AND, OR, EXOR GATE CHECK
925E 0E00 TYPE1: MVI C,00H ; SET GATE INPUTS
9260 79 LP1: MOV A,C
9261 F604 ORI 04H ; SET GATE OUTPUT 1
9263 47 MOV B,A ;STORE GATE INPUTS FOR I/P & O/P PINS IN REG B
9264 CDB192 CALL PROCESS
9267 0C INR C ; NEXT INPUT COMBINATION
9268 79 MOV A,C
9269 FE04 CPI 04H ; CHECK IF ALL INPUT COMBINATIONS ARE OVER
926B C26092 JNZ LP1
926E C3EB92 JMP GOOD ; OR JMP GOOD1
;BUFFER, INVERTER CHECK
9275 0E00 TYPE2: MVI C,00H ; SET GATE INPUT
9277 79 LP2: MOV A,C
9278 F602 ORI 02H ; SET GATE OUTPUT 1
927A 47 MOV B,A ; STORE GATE INPUT FOR I/P & O/P PINS IN B
927B CDB192 CALL PROCESS
Fig. 2: Control word logic diagram for mode
128