Specifications

CONSTRUCTION
ally via IC5 with the help of switches S1
(marked zero) and S2 (marked one). A
‘zero’ is entered by momentarily depress-
ing switch S1 alone, and a ‘one’ is en-
tered by depressing switch S1 momen-
tarily, after holding switch S2 in the
pressed condition.
The ‘D0’ bit of EPROM and ‘O0’ bit of
shift register (CD4035) are compared by
magnitude comparator (CD4585). If the
two data bits are equal, the output of com-
parator remains ‘high’ and it does not in-
terrupt/inhibit the operation of
monostable IC1 (NE555). However, if
there is a mismatch, the output of com-
parator goes ‘low’ and it inhibits IC1.
Thus, further data would not get entered
in the absence of clock pulse from IC1. If
data at each location of EPROM keeps
matching with the data input via switches
S1 and S2, the output of comparator
(at pin 3) will continue to stay ‘high’ to
keep IC1 enabled until all the bits of the
code have thus been compared. At the
end of the code, the tap A will be at logic
1, to energise relay RL1. If you have
by mistake entered wrong code via
switches S1 and S2, you can try again by
switching ‘off’ and then switching ‘on’
the circuit once again, using ‘on’/‘off’
switch S3.
Please note that for locking, the cir-
cuit need not play any role. The locking
operation could be performed manually.
Only for opening of the lock, this code
lock may be used. However, you are at
liberty to use the lock the other way
around.
An actual-size, single-sided PCB for
the circuit of Fig. 1 is shown in Fig. 2,
while Fig. 3 shows its component layout.
One may extend/modify the circuit by
utilising other seven unused data bits of
EPROM as well (presently only bit D0
has been used in this circuit).
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