Specifications

111
CONSTRUCTION
grounded in this circuit. With each
clock pulse from IC1, the counter IC2 out-
put increments by one and so also
the address of EPROM. Since the clock
pulses from IC1 are also being applied to
clock pin 6 of 4-bit shift register IC5
(CD4035), let us examine how the data
at its input pins 3, 4 (K, J) and output
pin 1 (O0) changes. Please note that O1
through O3 (at pins 15, 14 and 13 respec-
tively) of the shift register are not used
in this circuit.
On initial switching ‘on’ of power sup-
ply to the circuit, IC5 is reset due to the
power-on reset cir-
cuit comprising ca-
pacitor C5 and re-
sistor R6, connected
to its master reset
pin 5. Thus, ini-
tially its output O0
at pin 1 is at logic
0. On receipt of first
clock pulse from
IC1, the data pin
states of J and K
pins (4 and 3) get
shifted to output
pin 1. The logic
level at these two
pins (3 and 4) is
normally zero as
they are pulled to
ground via resistor
R3, when push to
‘on’ switch is in its
normal (off) posi-
tion. However, if
switch S2 is kept
pressed when clock
pulse is generated
by IC1 (by pressing
switch S1 momen-
tarily), logic 1 is
output to pin 1 of
shift register IC5.
In this circuit,
the final opening or
closing of lock is
achieved through
energisation of re-
lay RL1 via relay-driver transistor T1,
whose base is connected to either O2, O3,
O4, or O5 outputs of IC2 via resistor R7.
The selection of the position where point
A is to be connected would depend on the
binary digits in the code. If binary code is
of 4-bit length (equivalent to one hex
digit), then four clock pulses are needed
for advancing the EPROM address by four
locations. On fourth pulse, O2 will be at
logic 1 (unless IC1 gets disabled due to
non-matching of the code in comparator
CD4585, earlier) to energise relay RL1.
For 8-bit long code (equivalent to two hex
PARTS LIST
Semiconductors:
IC1 - NE 555 timer
IC2 - CD 4040 12-bit binary
counter
IC3 - 27C32 EPROM
IC4 - CD 4585 4-bit magnitude
comparator
IC5 - CD 4035 4-bit shift register
IC6 - 7805 regulator
T1, T2 - BC 547 npn transistor
Resistors (all ¼-watt, ±5% carbon, unless
stated otherwise):
R1, R5 - 10-kilo-ohm
R2 - 220-kilo-ohm
R3 - 2.2-kilo-ohm
R4 - 3.3-kilo-ohm
R6 - 15-kilo-ohm
R7, R8 - 1-kilo-ohm
Capacitors:
C1 - 1µ/10V electrolytic
C2, C4 - 0.01µ ceramic disk
C3 - 10µ/10V electrolytic
C5 - 22µ/10V electrolytic
C6 - 1000µ/16V electrolytic
Miscellaneous:
RL1 - 6V/100-ohm relay
S1, S2 - tactile switch
S3 - On/off switch
- DC power supply
(7.5V to 12V)
digits), the tap A needs to be connected
to O3. Similarly, for 16-bit code, point A
is to be connected to O4, and so on.
Operation
When the power supply to the circuit is
initially switched ‘on’, IC2 and IC5 are
reset, as explained earlier. Both A0 and
B0 inputs to IC4 are zero and thus its
output at pin 3 is ‘high’ and hence IC1 is
enabled. But, since pin 2 of IC1 is pulled
‘high’ via resistor R1, output of IC1 is
initially ‘low’. Initially, all ICs are in their
reset positions because of the capacitors
connected to their reset pins.
Assume that the required code num-
ber is lodged in the EPROM and point A
is joined to appropriate output of IC2 de-
pending on the length of lodged code, as
discussed in the description of relay op-
eration. Then, lock relay can be energised
by inputting the correct binary code seri-
Fig. 2: Acutal-size, single-sided PCB layout
Fig. 3: Component layout for the PCB
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