Specifications

CONSTRUCTION
EPROM-BASED PROGRAMMABLE
NUMBER LOCK
M
ost of the code lock/number lock
circuits presented in EFY so far
have been based on discrete
TTL and/or CMOS ICs.
This circuit is based on
a familiar EPROM
27C32, wherein the re-
quired code is stored. It
is a number lock, which
can be programmed to
any coded number. The
length of the number
can also vary.
To make a code-
lock for a particular
number (octal, decimal,
or hexadecimal), that
number is first con-
verted to its binary
equivalent. It is then
entered bit-by-bit into
consecutive memory lo-
cations of EPROM 2732
(IC3), starting with the
MSB and ending with
the LSB (D0). Assume
that the required num-
ber is 12 (hex). Its
equivalent binary num-
ber is 00010010. This
binary number is en-
tered into the EPROM
at memory locations
starting with 001(hex),
as shown in Table I. The first memory
location is always loaded with binary byte
XXXXXXX0 (here, X means “do not care”).
The data is stored in consecutive loca-
tions, starting with location 001H, as
stated earlier.
Description
The circuit comprises six ICs, inclu-
ding the EPROM and the voltage regula-
tor. IC1 is a timer NE555, which is
configured as a monostable flip-flop.
JUNOMON ABRAHAM
Please note that its reset pin 4 is con-
nected to output A = B (O
A=B
) pin 3 of
comparator IC4 (CD4585). Thus, as long
as 4-bit
magni-
tude of
input A
to IC4 is
equal to
4-bit
magni-
tude of
the other
input B
(to IC4),
its output
pin 3 is at logic 1 and thus monostable
IC1 is enabled. When magnitude of input
A is not equal to B, the output pin 3 of
IC4 is at logic 0 and as a result IC1 is
disabled.
In enabled state, the monostable IC1
generates an output pulse when switch
S1 (marked zero) is momentarily pressed.
This output pulse from IC1 is used as a
clock pulse for counter IC2 and shift reg-
ister IC5. While IC2 counts on high-to-
low transition of the clock, IC5 shifts on
low-to-high going transition of the clock.
Hence, to synchronise the operation of IC2
and IC5, the clock pulse to IC2 is inverted
by the transistorised inverter stage
around transistor T1.
At power on, IC2 is reset due to power-
on-reset circuit built using capacitor C3
and resistor R5. Hence, all its outputs
(including O0 through O5 connected to
addresses A0 through A5 of EPROM IC3)
are initially at logic 0. In other words,
initial address selection for EPROM is
000H, since address lines A6 through A11
of EPROM 27C32 are permanently
RUPANJANA
TABLE I
Memory Data
address Hex Binary
(Hex) Equivalent
000 X0 XXXXXXX0
001 X0 XXXXXXX0
002 X0 XXXXXXX0
003 X0 XXXXXXX0
004 X1 XXXXXXX1
005 X0 XXXXXXX0
006 X0 XXXXXXX0
007 X1 XXXXXXX1
008 X0 XXXXXXX0
Note: X means do not care
Fig. 1: Complete circuit diagram of number lock
110