Installation guide

read back and compared. This process is repeated with the data inverted.
This is then repeated for each location.
Action/Possible faults
Check that the BRAM shorting link is in the correct position.
Faulty BRAM circuitry.
IUSCC Test
This test checks that each IUSCC may be accessed, and that read and write
cycles operate correctly.
Action/Possible faults
Faulty IUSCC or associated circuitry.
PTM Test
A simple read/write access test. The device is initialised and then the data
55AAAA55 is written to the counter register. It is read back and compared
before the process is repeated with the data inverted.
Action/Possible faults
Faulty PTM or associated circuitry.
SCC Test
A simple read/write access test. The data 55 is written to the counter low
byte register. It is read back and compared before being inverted and the
process repeated.
Action/Possible faults
Faulty SCC or associated circuitry.
Exception Fault
It is possible that faulty hardware may generate invalid exceptions and
terminate proceedings with an exception error display.
X870-300451 Issue 2 2-9 Rev.0