Specifications

X723-300151 4-9 Issue 2
1 2 3 4 5 6 7
DEST
B4
M1
M2
M1
M2
M1
M2
M1
M2
X1
B5 B7 B7 B6 X2
B5
X3
X4
M1
M2
M3
M4
B1
B4B5
B6
B4
X4
B5
X4
B4
X4
B4
B7
B8
M1
X3
M2
M1
M2
X4
M1
M2
M1
M2
1 2 3 4 5 6 7
DEST
M3
M4
B6
M3
M4
M3
M4
M3
M4
X1
B7 B5 B5 B4
X2
B5
X3
X4
M1
M2
M3
M4
B1
B6B7
B6
B6
X2
B7
X2
B4
B7
B8
M3
M4
X1
LINE 2 - PATCHLINE 1 - PATCH
X2
X4
X3
X3
X3
X1
X2
M3
M4
X1
M3
M4
M3
M4
M3
M4
B6
X2
X1
M1
M2
Table 4-2 Dual LIU Patchfield DT995D
Notes:
1. A space in the table above indicates a fixed '1' condition
2. Where more than one source is shown these are logically 'ANDed' to
the destination.
3. X1, X2, X3 and X4 are Dual LIU patchfield cross-connect bits.
4. M1, M2, M3 and M4 are bits on the management 'M' busses.
5. B1, B4, B5, B6, B7 and B8 are spare bits in the TS0 Non Frame Word.