Specifications

BASIC Stamp II Application Notes
Parallax, Inc. • BASIC Stamp Programming Manual 1.8 • Page 355
2
Shiftout, plus one more, the relationship of valid data to clock pulses.
Some devices latch bits onto the serial data output on the rising edge of
the clock line. Output bits remain valid until the next rising edge. In
these cases, your program must specify post-clock input for the Shiftin
mode. When bits are latched on the falling edge of the clock, specify pre-
clock input.
With pre-clock input, we sometimes encounter a chicken-and-egg
problem. How can the first bit be clocked out before the first clock pulse?
It can’t, of course. The simple solution is to specify one additional bit in
the Shiftin instruction.
However, most serial peripherals require that some instructions be sent
to them before they return any data. In this case, the falling edge of the
last Shiftout clock cycle clocks the first bit of the following pre-clock
Shiftin instruction.
Serial ADC with Shiftout and Shiftin. The third example (figure 6,
listing 3) uses Shiftout and Shiftin to hold a two-way conversation with
an LTC1298 ADC. An initial Shiftout sends configuration bits to the
LTC1298 to select channel and mode, then a Shiftin gets the 12-bit result
of the conversion. The program listing concentrates on the mechanics of
the Shift instructions; for more detailed information on the ADC itself,
see Stamp Application Note #22 or the manufacturer’s spec sheet.
1k
+5
10µF
tantalum
+
5k
pot
5k
pot
+5
BS2
pin 0
BS2
pin 2
BS2
pin 1
Variable Voltage
Source for Demo
0–5V in
CS
CH0
CH1
GND
Vcc
CLK
Dout
Din
LTC1298
1
Figure 6. Schematic for LTC 1298. BS 2.
2: Using Shiftin & Shiftout