Specifications

BASIC Stamp II Application Notes
Page 352 • BASIC Stamp Programming Manual 1.8 • Parallax, Inc.
flop is described as “latching” Data
onto Q. Parallel latches, like the
one shown in figure 1, allow sev-
eral bits to be simultaneously
latched onto a set of outputs. This
is one of the ways that a computer
addresses multiple devices on a
single parallel data bus—it puts
the data on the bus, then triggers
one device’s Clock. The data is
latched into the destination de-
vice only; other devices ignore the
data until their Clock lines are trig-
gered.
With different wiring, the parallel
latch becomes a serial one, known
as a shift register (figure 2). See
how this works: When a rising edge appears on the Clock input, all of
the flip-flops latch their Data inputs to their Q outputs. Because they are
wired in a chain with each Q output connected to the next flip-flop’s
Data input, incoming bits ripple down the shift register.
You can picture this process as working like a bucket brigade or a line
of people moving sandbags. In perfect coordination, each person hands
their burden to the next person in line and accepts a new one from the
previous person.
Looking at this from the standpoint of the parallel output, there’s a
potential problem. When data is being clocked into the shift register, the
data at the output isn’t stable—it’s rippling down the line. The cure for
this is to add the previously described parallel latch after the shift
register, and clock it only when we’re finished shifting data in. That’s
the arrangement shown in figure 3.
It isn’t too much of a stretch to imagine how this kind of circuit could be
turned around and used as an input. Data would be grabbed in parallel
by a latch, then transferred to a shift register to be moved one bit at a
time to a serial data output.
QD
CLK
FF0
QD
CLK
FF1
QD
CLK
FF2
QD
CLK
FF3
Serial
Data In
Parallel
Data Out
Shift
Clock
Figure 2. Serial shift register.
2: Using Shiftin & Shiftout