Specifications

BASIC Stamp II
Parallax, Inc. • BASIC Stamp Programming Manual 1.8 • Page 329
2
used by controller peripherals like ADCs, DACs, clocks, memory
devices, etc. Trade names for synchronous-serial protocols include SPI
and Microwire.
At their heart, synchronous-serial devices are essentially shift-regis-
ters—trains of flip-flops that pass data bits along in a bucket-brigade
fashion to a single data-output pin. Another bit is output each time the
appropriate edge (rising or falling, depending on the device) appears
on the clock line. BS2 application note #2 explains shift-register opera-
tion in detail.
A single Shiftin instruction causes the following sequence of events:
Makes the clock pin (cpin) output low.
Makes the data pin (dpin) an input.
Copies the state of the data bit into the msb (lsb- modes) or lsb (msb-
modes) either before (-pre modes) or after (-post modes) the clock
pulse.
Pulses the clock pin high for 14µs.
Shifts the bits of the result left (msb- modes) or right (lsb-modes).
Repeats the appropriate sequence of getting data bits, pulsing the
clock pin, and shifting the result until the specified number of bits
is shifted into the variable.
Making Shiftin work with a particular device is a matter of matching
the mode and number of bits to that device’s protocol. Most manufac-
turers use a timing diagram to illustrate the relationship of clock and
data. Figure I-25a shows Shiftin’s timing. For instance, we can use
Shiftin to acquire the bits generated by a toggle flip-flop, as shown in
figure I-25b. This makes a good example because we know exactly what
IC = 1/2 of a 4013 dual D flip-flop wired as a toggle FF
Shiftin Timing Diagram Circuit for Shiftin Demo
10k
CLK
DQ
Q
7,8,10
14
12
9
11 13
+5V
pin1
(cpin)
pin0
(dpin)
14µs
Clock
(cpin)
Data
(dpin)
–46µs–
-pre modes
sample data
clock pulse
-post modes
sample data
clock pulse
afterbefore
ab
Figure I-25