Technical data

Host interface 26/72

netRAPID Chip Carrier | Design Guide

4.4 Serial dual-port memory mode

The netRAPIDs offer a serial dual-port memory interface, which is a SPI Slave interface. The

supported mode is clock idle state high with sampling on the trailing clock edge (SPI mode 3).

The Serial Peripheral Interface (SPI) is a bus system for the synchronous serial communication of

digital electronic circuits allowing versatile applications. It is based on the master-slave-principle.

The general connection of the serial dual-port memory to any SPI capable host CPU is shown in

the following figure.

Figure 12: Serial dual-port memory interface

For the pinning of netRAPID, see Table 4 on page 19.

Activating the serial dual-port memory mode

The serial dual-port memory mode is activated by a pull-down resistor as described in section Host

interface m

ode on page 21.

Timing diagram serial dual-port memory

interface

To access the serial dual-port memory,

 see timing diagram in section Serial IO Mode Timing in the document Technical Data

Reference Guide, netX 10 (reference [2]),

 see timing diagram in section Serial IO Mode Tim

ing in the document Technical Data

Reference Guide, netX 51/52 (reference [3]).

Softw

are implementation and protocol

A protocol contains an address, a function identifier (read/write), a length information and data to

access to the dual-port memory.

For information about the software implementation and the protocol see section Host Software

Implementation and section Serial DPM Protocol Description in the document Serial Dual-Port

Memory Interface, see reference [1].

Important:

The host application has to do two read commands to initialize the serial dual-port

memory communication (SPI). Any address can be used.