Technical data

Host interface 25/72
netRAPID Chip Carrier | Design Guide
DOC111004DG04EN | Revision 4 | English | 2014-09 | Released | Public © Hilscher, 2013-2014
The following table gives the values for the timing parameters for netRAPID devices. For
exchangeability of netRAPID NRP 52 with netRAPID NRP 10 devices and visa versa use the
values of column Common of Table 8.
Symbol Description netRAPID 10
netX 10
netRAPID 52
netX 52
Common
t
1
tAS min. Minimum address setup time 0 ns 0 ns 2 ns
t
2
tBV max. Maximum time from cycle start
until BUSYn signal is valid
5.7 ns 5.7 ns 40 ns
tBAR typ.
Typical BUSY active time (read access)
- - - t
3
tBAR max.
See important note 1
68 ns 68 ns -
tBAW min. Minimum BUSY active time (write access) 0 ns 0 ns 0 ns t
4
tBAW max.
See important note 1
68 ns 68 ns -
t
5
tDVR min. Minimum time between valid data bus signals
and rising edge of BUSYn signal
7.8 ns 7.8 ns 5 ns
t
6
tDSW min. Minimum setup time for write data 10.8 ns 12.8 ns 25 ns
t
7
tDHR min. Minimum read data hold time 2.1 ns 2.1 ns 0 ns
t
8
tDHW min. Minimum hold time for write data 0.8 ns 2.8 ns 2.8 ns
t
9
tAHR min. Minimum address hold time 0 ns 0 ns 0 ns
t
10
tAHW min. Minimum address hold time 0.9 ns 2.9 ns 2.9 ns
t
11
tRWI Minimum inactive time for RDn or WRn 10.5 ns 12.5 ns 12.5 ns
Table 8: Symbols for netRAPID timing diagram for read and write access
Important note 1: Avoid dual-port memory access errors
It is mandatory that the host CPU always uses the BUSYn signal, otherwise this
results in wrong data read from the dual-port memory or dual-port memory write
accesses are ignored.
 For maximum performance, the BUSYn signal must always be evaluated by the
host CPU.
Note 2: The value for tBAR typ. (t
3
typ.) depends on the used firmware/application on the netX.
Note 3: DPM_BHEn (pin 35) only used for 16 bit interface.