Technical data

Host interface 24/72
netRAPID Chip Carrier | Design Guide
DOC111004DG04EN | Revision 4 | English | 2014-09 | Released | Public © Hilscher, 2013-2014
4.3.5 Timing diagram dual-port memory interface
The following diagram shows the timing for dual-port memory read access.
Figure 10: Timing diagram for read access
The following diagram shows the timing for dual-port memory write access.
Figure 11: Timing diagram for write access
Description and values are on the next page.