Technical data

Host interface 23/72

netRAPID Chip Carrier | Design Guide

In case of a 16-bit system you have to generate the DPM_BHEn (pin 35) and DPM_A0 (pin 20)

signal according to the following table.

DPM_BHEn DPM_A0 Function

0 0 word access

0 1 access high byte

1 0 access low byte

1 1 no access

Table 7: Function table of the 16-bit decode logic

4.3.2 Dual-port memory control lines

Integration of the netRAPID is done by mapping the memory space of the dual port memory into

the address range of the host system.

The access to the dual-port memory is handled over the control lines DPM_WRn (pin 37, write),

DPM_RDn (pin 36, read) and DPM_CSn (pin 34, Chip select) and could be like standard static RAM.

All signals are low active.

4.3.3 Interrupt line to the host system

The signal DPM_DIRQn (located at pin 39, also used as mode discrimination signal) can be used to

generate an interrupt to the host system when the netX processor of the netRAPID writes into the

specific handshake cells of the dual-port memory. These cells are used for synchronization of the

netRAPID and the host system and have handshake bits. The interrupt will be cleared if the host

reads the handshake cell that was written from the netX of the netRAPID.

Important: In interrupt mode, when an 8-bit host performs a read access to any of the

16-bit wide handshake registers, the netX releases the interrupt as soon as the high byte

or the low byte was read. The read order (high byte first or low byte first) is irrelevant. An

8-bit host shall use polling mode instead of interrupt mode!

Important: Never drive the signal DPM_DIRQn (pin 39). Instead, operation with pull-down

and pull-up resistors is recommended.

4.3.4 Busy line to the host system

The signal DPM_BUSYn is used to insert wait states into a current access from host system to a

netRAPID. When the signal is active the host must wait for the current transfer.

Also see the timing diagram in section Timing diagram dual-port memory interface on page 24.