Technical data

Host interface 21/72

netRAPID Chip Carrier | Design Guide

4.2.3 Boot signal and boot options

Mandatory: Always add a push button or switch (or an equivalent device) to your host system

connected to the netRAPID device to activate the serial boot mode of the ROM loader. The serial

boot mode is necessary for your production to load the Second Stage Boot Loader into the

netRAPID device or later for support to be able to update the Second Stage Boot Loader. If you do

not implement a push button or switch (or an equivalent device) to your host system, you will not

be able to load or update the Second Stage Boot Loader! With NRP 52 devices without a Second

Stage Boot Loader activate the Ethernet boot mode by default which is not supported.

For details about the circuit for the host system see Figure 21: Schematic NRPEB-CCS and

NRPEB-DPS (Part 1) on page 62 or see Figure 23: Schematic NRPEB-RE2 (Part 1) on page 64.

Note:

If you want to make use of the other boot options that the netRAPID offers, you need to

implement two DIP switches or an equivalent device for switching two signals (RUN

and RDY).

Note: To serial boot mode requires an USB interface or a serial (UART) interface.

Activating the boot mode

The boot signal is located at pin 60 (RDY). After a reset it is an input signal and active low. To

activate the boot mode, pin 60 has to be connected via 390  to GND (low signal) after a reset.

Note: The signal level during the reset and shortly afterwards must be low in order to force

the netRAPID into the boot mode.

4.2.4 Host interface mode

netRAPIDs support two host interface modes

 parallel dual-port memory and

 serial dual-port memory (SPI).

The host interface mode is evaluated by the Second Stage Boot Loader during boot. The Second

Stage Boot Loader uses this setting to initialize the selected dual-port memory mode in the host

interface.

Activating the parallel dual-port memory mode

 A high signal at DPM_DIRQn (pin 39) activates the dual-port memory mode (via a 2.2 k pull-

up resistor or the input is open).

 The data width of the dual-port memory can be set to 8 or 16 bit. The data width is set at

DPM_SIRQn (pin 40) during the start-up phase.

 A high signal at DPM_SIRQn (via a 2.2 k pull-up resistor or the input is open) sets the

data width of 8 bit.

 A low signal at DPM_SIRQn (via a 2.2 k pull-down resistor) sets the data width of 16

bit.