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Design Guide

netRAPID Chip Carrier

Hilscher Gesellschaft für Systemautomation mbH

www.hilscher.com

Summary of content (72 pages)

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Design Guide netRAPID Chip Carrier Hilscher Gesellschaft für Systemautomation mbH www.hilscher.
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Introduction 2/72 Table of Contents 1 Introduction.............................................................................................................................................4 1.1 About this document ......................................................................................................................4 1.1.1 List of revisions.................................................................................................................................. 4 1.1.
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Introduction 7 3/72 Evaluation Boards................................................................................................................................39 7.1 Evaluation Board NRPEB-CCS and NRPEB-DPS ......................................................................39 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.2 Fieldbus measuring points (X3) ....................................................................................................... 40 PROFIBUS DP (X30) ................................
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Introduction 1 4/72 Introduction 1.1 About this document This design guide describes the mechanical and electrical interfaces of netRAPID products. This document includes the description of the netRAPID Evaluation Boards. 1.1.1 List of revisions Rev Date Name Chapter Revision 2 2013-12-16 HH All Description of NRP 10-DPS, NRP 10-CCS and NRP 52-RE. 3 2014-07-30 HH 2 Section Product overview expanded. 4 2014-09-16 HH 3.
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Introduction 1.2 1.2.1 5/72 Legal notes Copyright © Hilscher, 2013-2014, Hilscher Gesellschaft für Systemautomation mbH All rights reserved. The images, photographs and texts in the accompanying material (user manual, accompanying texts, documentation, etc.) are protected by German and international copyright law as well as international trade and protection provisions.
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Introduction 1.2.3 6/72 Exclusion of liability The software was produced and tested with utmost care by Hilscher Gesellschaft für Systemautomation mbH and is made available as is. No warranty can be assumed for the performance and flawlessness of the software for all usage conditions and cases and for the results produced when utilized by the user.
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Product overview 2 7/72 Product overview netRAPID chip carriers are for easy and fast integration into a host system:  Fully functional 32 x 32 mm chip carrier that can be soldered directly on a PCB of the host system,  for a direct network connection, only a connector on PCB is needed,  parallel dual-port memory or serial dual-port memory (fast SPI slave interface),  LEDs,  address switches.
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Product overview 8/72 2. Three netRAPID devices are included the netRAPID Evaluation Board. Create your host system and simply solder the netRAPID device onto your host system manually and have your first prototype done. 3. Start your series SMD production of your host system with netRAPID devices from a tray containing 24 pcs. Figure 2: netRAPID tray containing 24 pcs. for series production Overview Products Description Part no Evaluation board including NRP 10-CCS 7600.
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Product overview 9/72 Interface overview The subsequent table lists interfaces and functions of the netRAPID Chip Carriers which are currently supported by the licensed netRAPID Standard Loadable Firmware (NRPLFW). Note that customized netRAPID firmware with extra functionalities will be available from Hilscher on request.
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Product overview 2.1 2.1.1 10/72 Block diagrams NRP 10-CCS Figure 3: NRP 10-CCS block diagram 2.1.
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Product overview 2.1.
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Mechanics 3 12/72 Mechanics 3.1 Dimension A netRAPID has the following dimensions: L= 32 mm, W = 32 mm and H = 4 mm. 3.2 3.2.1 Design guidelines for the host system Footprint The layout for the netRAPID footprint on the host system requires the following dimensions. There is one footprint for NRP 10 chip carriers and one for NRP 52 chip carriers.
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Mechanics 13/72 Figure 7: Footprint NRP 52 3.2.2 Thermal behavior and thermal pad NRP 10 devices have a power consumption of 1 - 1.2 W and NRP 52 devices of 1.8 W, which generates heat. The generated heat must be dissipated to prevent overheating of the chip.
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Mechanics 14/72 This results in requirements for the PCB of the host system:  Use at least 9 vias, which are to be connected to ground plane.  Use a large copper surface on the PCB of the host system to reach a good heat dissipation for the netRAPID.  Don’t place components on the PCB of the host system below the netRAPID to avoid heat dissipation of other component than netRAPID. The thermal pad of the netRAPID device has GND potential.
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Mechanics 15/72 Soldering netRAPID devices can be placed on the PCB of the host system for SMD production. netRAPID can be picked and placed (from the tray to the PCB of the host system) using asymmetric suck in. Place netRAPID on the top side of the PCB of the host system. Important note: The thermal profile for reflow soldering depends on the used soldering paste and the used reflow system. Read the data sheet of the manufacturer of the used soldering paste for requirements to the thermal profile.
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Mechanics 3.4 16/72 Matrix label A matrix label is on the device for identification. It contains 3 items: 1. Part number 2. Hardware revision 3. Serial number The figure shows part number 7600.100, hardware revision 2 and serial number 20000.
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Host interface 4 4.
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Host interface Pin Signal 39 DPM_DIRQ 18/72 Specification Function I50KU During start up: Setting of Host Interface Mode (see section Host interface mode on page 21). Other shared Signals HIFM0 I50KU Host Interface Mode 0 During runtime: Dual-Port Memory Data Interrupt. 40 DPM_SIRQ HIFM1 I50KU I50KU During start up: Setting of Host Interface Mode (see section Host interface mode on page 21). Host Interface Mode 1 During runtime: Dual-Port Memory Synchronization Interrupt.
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Host interface Pin 19/72 Signal Specification Function TXN0 Ethernet specific Ethernet channel 0 transmit negative FB4 Field bus specific Field bus connector pin 4 TXP0 Ethernet specific Ethernet channel 0 transmit positive Other shared Signals 71 72 73 74 75 76 FB5 Field bus specific Field bus connector pin 5 - Ethernet specific - FB6 Field bus specific Field bus connector pin 6 RXN1 Ethernet specific Ethernet channel 1 receive positive FB7 Field bus specific Field bus connect
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Host interface 4.2 4.2.1 20/72 General signals Supply voltage Only a single 3.3 V operation voltage is needed to operate the netRAPID. The voltage must be regulated and can have a tolerance of ±5% (3.15 - 3.45 V) and must be connected twice to the netRAPID chip carrier. The power has to be supplied between pins +3V3 and GND. To avoid EMI problems use bypass capacitors in the power supply path. All other special voltages required on the netRAPID are generated by onboard DC/DC converters.
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Host interface 4.2.3 21/72 Boot signal and boot options Mandatory: Always add a push button or switch (or an equivalent device) to your host system connected to the netRAPID device to activate the serial boot mode of the ROM loader. The serial boot mode is necessary for your production to load the Second Stage Boot Loader into the netRAPID device or later for support to be able to update the Second Stage Boot Loader.
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Host interface 22/72 Activating the serial dual-port memory mode (SPI) A low signal at DPM_DIRQn activates the SPI mode (via a 2.2 kΩ pull-down resistor). netRAPID internal pull-up and pull-down resistors Pin Signal netX 10 on NRP 10 netX 52 on NRP 52 39 DPM_DIRQn 50 kΩ pull-up 50 kΩ pull-up 40 DPM_SIRQn 50 kΩ pull-up 50 kΩ pull-down Important: Never drive the host interface mode signal (DPM_DIRQn pin 39). Instead, operation with pull-down and pull-up resistors is recommended. 4.
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Host interface 23/72 In case of a 16-bit system you have to generate the DPM_BHEn (pin 35) and DPM_A0 (pin 20) signal according to the following table. DPM_BHEn DPM_A0 Function 0 0 word access 0 1 access high byte 1 0 access low byte 1 1 no access Table 7: Function table of the 16-bit decode logic 4.3.2 Dual-port memory control lines Integration of the netRAPID is done by mapping the memory space of the dual port memory into the address range of the host system.
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Host interface 4.3.5 24/72 Timing diagram dual-port memory interface The following diagram shows the timing for dual-port memory read access. Figure 10: Timing diagram for read access The following diagram shows the timing for dual-port memory write access. Figure 11: Timing diagram for write access Description and values are on the next page.
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Host interface 25/72 The following table gives the values for the timing parameters for netRAPID devices. For exchangeability of netRAPID NRP 52 with netRAPID NRP 10 devices and visa versa use the values of column Common of Table 8. Symbol Description netRAPID 10 netRAPID 52 Common netX 10 netX 52 t1 tAS min. Minimum address setup time 0 ns 0 ns 2 ns t2 tBV max. Maximum time from cycle start until BUSYn signal is valid 5.7 ns 5.7 ns 40 ns t3 tBAR typ.
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Host interface 4.4 26/72 Serial dual-port memory mode The netRAPIDs offer a serial dual-port memory interface, which is a SPI Slave interface. The supported mode is clock idle state high with sampling on the trailing clock edge (SPI mode 3). The Serial Peripheral Interface (SPI) is a bus system for the synchronous serial communication of digital electronic circuits allowing versatile applications. It is based on the master-slave-principle.
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Diagnostic interface 5 27/72 Diagnostic interface The diagnostic interface can be used for  configuration download,  diagnostic purposes and  firmware update (firmware update at netRAPID NRP 10 only) It is mandatory to add a diagnostic interface to the host system. This interface is needed during the production process to load the Second Stage Boot Loader and firmware into the netRAPID device. 5.
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Diagnostic interface 5.2 28/72 Serial interface – UART The pins of the UART interface are shared with the pins for the SYNC interface. The standard firmware activates the SYNC interface and deactivates the UART by default. Note: The following pins of the netRAPID relate to the serial interface (UART). The table provides the signal names: Pin Name Shared with 42 UART_RX SYNC0 43 UART_TX SYNC1 Table 10: Pin assignment to serial interface (UART) The signals UART_RX and UART_TX have LVTTL level.
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Device type specific interfaces 6 29/72 Device type specific interfaces 6.1 6.1.
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Device type specific interfaces 6.1.2 30/72 CC-Link interface The pin assignment for CC-Link: Pin Signal CC-Link Signal 68 FB1 DA 69 FB2 DB 70 FB3 DG 71 FB4 SLD 72 FB5 FG 73 FB6 not connected 74 FB7 not connected 75 FB8 not connected 76 FB9 not connected Table 11: Pin assignment CC-Link interface of NRP 10-CCS It is also strongly recommended to keep the length for the signal lines below 30 mm and to take EMC aspects into account.
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Device type specific interfaces 6.1.4 31/72 Address and baud rate switches The CC-Link Slave firmware reads the position of three switches to configure the CC-Link station address and the baud rate.
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Device type specific interfaces 6.2 6.2.
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Device type specific interfaces 6.2.2 33/72 PROFIBUS DP interface The pin assignment for PROFIBUS DP: Pin Signal PROFIBUS DP Signal 68 FB1 ISO GND 69 FB2 CNTR-P 70 FB3 Rx/Tx+ 71 FB4 not connected 72 FB5 not connected 73 FB6 not connected 74 FB7 Rx/Tx- 75 FB8 not connected 76 FB9 VP Table 14: Pin assignment PROFIBUS DP interface of NRP 10-DPS It is also strongly recommended to keep the length for the signal lines below 30 mm and to take EMC aspects into account.
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Device type specific interfaces 6.2.4 34/72 Switches The PROFIBUS DP Slave firmware reads the position of two address switches to configure the PROFIBUS station address.
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Device type specific interfaces 6.3 6.3.
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Device type specific interfaces 6.3.2 36/72 Ethernet interface The pin assignment for Ethernet: Pin Signal Ethernet Signal 68 FB1 RXN0 69 FB2 RXP0 70 FB3 TXN0 71 FB4 TXP0 72 FB5 not connected 73 FB6 RXN1 74 FB7 RXP1 75 FB8 TXN1 76 FB9 TXP1 Table 17: Pin assignment Ethernet interface of NRP 52-RE It is also strongly recommended to keep the length for the signal lines below 30 mm and to take EMC aspects into account.
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Device type specific interfaces 37/72 6.3.4 Switches Note: Address switches are for future use, as the Ethernet firmware does not read the positions of the switches.
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Device type specific interfaces 6.3.5 38/72 SYNC The pins of the SYNC interface are shared with the pins for the UART interface. By default the SYNC interface is activated and UART is deactivated in the standard firmware. Note: Pin Name Shared with 42 SYNC0 UART_RX 43 SYNC1 UART_TX Table 20: Pin assignment to SYNC interface The SYNC Signal has LVTTL level. A maximum load of 6 mA may not be exceeded.
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Evaluation Boards 7 39/72 Evaluation Boards 7.1 Evaluation Board NRPEB-CCS and NRPEB-DPS Figure 16: Evaluation Board NRPEB-CCS and NRPEB-DPS No.
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Evaluation Boards No.
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Evaluation Boards 7.1.3 41/72 CC-Link (X50) CC-Link pin assignment CC-Link Pin Signal Description 1 FB1 / DA Data positive 2 FB2 / DB Data negative 3 FB3 / DG Data ground, to ISO_GND, 3.3 nF against PE 4 FB4 / SLD Shield, Pin 4 and Pin 5 are connected internally 5 FB5 / FG Fieldground, Pin 4 and Pin 5 are connected internally and are on PE COMBICON male connector Table 25: CC-Link pin assignment Position in Figure 16 on page 39. 7.1.
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Evaluation Boards 7.1.5 42/72 Address switches (S1, S2) for PROFIBUS DP The following table shows the meaning of the switches. PROFIBUS DP Station address Slave S2, position on page 39. in Figure 16 S1, position on page 39. Station address = Value * 10 Value range for Station address: 0, 1, …, 8, 9 = valid address + in Figure 16 Value * 1 0, 1, …, 8, 9 = valid address 0 … 99 Table 28: Meaning of the address switch (PROFIBUS DP) Example: For station address 12 set S2 to 1 and S1 to 2.
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Evaluation Boards 7.2 43/72 Evaluation Board NRPEB-RE2 Figure 17: Evaluation Board NRPEB-RE2 Positions 16 and 18 are left out to keep identical numbering with the NRPEB-CCS and NRPEB-DPS. Note: No.
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Evaluation Boards No. in 44/72 Name Description Page X2 Host interface measuring points 48 X11 JTAG interface, foil connector (for Hilscher development and production only) 52 - - - X50 Ethernet interface (RJ45 socket) 40 - - - S1 Address switch Station address * 1 44 S2 Address switch Station address * 10 figure - - Table 29: Positions on NRPEB-RE2 7.2.
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Evaluation Boards 7.3 7.3.1 T1 45/72 Operating elements of Evaluation Boards Reset button (T1) Function Resets the chip carrier. When pressed, pin 41 is connected to GND. Table 31: Reset button T1 Position in Figure 16 on page 39. 7.3.2 S-Boot button (T2) T2 Function Activating the serial boot mode via UART or USB. This signal is evaluated after a reset of the chip during start-up phase. In serial boot mode, communication from the boot wizard application to the chip is possible.
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Evaluation Boards 7.4 7.4.1 46/72 Interfaces Host interface (X1) Connector X1 has the signals of the host interface. X1 is a 64-pin connector. X1 Pin Signal Pin Description (chip carrier) 1 +3V3 - +3.
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Evaluation Boards X1 Pin 47/72 Signal Pin Description (chip carrier) 41 DPM_A8 28 Dual-Port Memory Address 8 42 DPM_A7 27 Dual-Port Memory Address 7 43 DPM_A6 26 Dual-Port Memory Address 6 44 DPM_A5 25 Dual-Port Memory Address 5 45 DPM_A4 24 Dual-Port Memory Address 4 46 DPM_A3 23 Dual-Port Memory Address 3 47 DPM_A2 22 Dual-Port Memory Address 2 48 DPM_A1 21 Dual-Port Memory Address 1 49 DPM_A0 20 Dual-Port Memory Address 0 50 GND - Ground 51 DPM_D15 17 Dual-
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Evaluation Boards 7.4.2 48/72 Host interface measuring pins (X2) Connector X2 has the signals of the host interface. X2 is a 40-pin connector.
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Evaluation Boards X2 49/72 Pin Signal Pin (chip Description 38 DPM_D0 39 +3V3 +3.3V Power Supply 40 GND Ground carrier) 2 Dual-Port Memory Data 0 Table 34: Pin assignment X2 Position in Figure 16 on page 39 or Figure 17 on page 43. 7.4.
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Evaluation Boards 7.4.4 X5 50/72 Host interface mode (X5) Pin Signal Pin Description (chip carrier) 1 Low via 2.2 kΩ to GND 2 Low via 2.2 kΩ to GND 3 DPM_STRQ 40 4 DPM_DIRQ 39 5 open 6 open Table 36: Pin Assignment X5 Position in Figure 16 on page 39 or Figure 17 on page 43. Set host interface Use a jumper to set the host interface mode. The mode is read during the start-up phase. If parallel dual-port memory mode is set, then the data width of 8 or 16 bit has to be selected.
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Evaluation Boards 7.4.5 51/72 USB interface (X6) mini USB jack Pin Signal USB Pin Description Device 1 2 D- 44 Data –; has to be protected with a 22 Ω resistor. 3 D+ 45 Data +; has to be protected with a 22 Ω resistor. 4 5 Position GND Ground in Figure 16 on page 39 repectively Figure 17 on page 43.
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Evaluation Boards 7.4.6 X5 52/72 JTAG connector (X11) Pin Signal 1 +3.3 V 2 BSCAN_TRST# 3 JT_TCK 4 JT_TDO 5 JT_TD1 6 JT_TMS 7 JT_TRSTN 8 GND Table 38: Pin assignment JTAG connector NXAC-JTAG Interface: Connector: SEK-18 SV MA LP STR29 20P PL3 to film Dimensions: 43.2 x 43.2 mm Interface not isolated Order Number: 2400.
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Evaluation Boards 7.4.7 53/72 Power supply (X100) The Evaluation board has to be supplied by DC. VIN is from 18 V to 30 V. The typical supply voltage is 24 V. Pin Description 1 GND Ground 2 VIN 18 - 30 V DC The evaluation board supplies the netRAPID device with 3.3 V operating voltage. Position in Figure 16 on page 39 respectively Figure 17 on page 43. The connection for the power supply is suitable for the power supply NXAC-Power.
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Technical data 8 54/72 Technical data 8.1 CC-Link 8.1.1 netRAPID Chip Carrier NRP 10-CCS NRP 10-CCS Parameter Value Device identification Part number 7650.
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Technical data 8.1.2 55/72 Evaluation Board NRPEB-CCS NRPEB-CCS Parameter Value Device identification Part number 7600.
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Technical data 8.2 56/72 PROFIBUS DP Slave 8.2.1 netRAPID Chip Carrier NRP 10-DPS NRP 10-DPS Parameter Value Device identification Part number 7650.
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Technical data 8.2.2 57/72 Evaluation Board NRPEB-DPS NRPEB-DPS Parameter Value Device identification Part number 7600.
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Technical data 8.3 58/72 Real-Time Ethernet 8.3.1 netRAPID Chip Carrier NRP 52-RE NRP 52-RE Parameter Value Device identification Part number 7670.
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Technical data 8.3.2 59/72 Evaluation Board NRPEB-RE2 NRPEB-RE2 Parameter Value Device identification Part number 7600.
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Technical data 8.4 60/72 Signals Input / Output Min. Typ. Max. Unit VIH 2.0 3.3 3.6 V VIL 0 0.8 V 10 µA Binary input DI Ili Binary output DO VOH Notice: Outputs are not overload protected! 2.4 IOH VCC-0.
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Schematics 9 61/72 Schematics 9.1 Overview This chapter contains the schematics of the Evaluation Boards. The schematics are an example for the host system. The host CPU, which is a standard PC, is connected via a PC adapter card to the host interface connector (X1).
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Schematics 9.
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Schematics 63/72 Figure 22: Schematic NRPEB-CCS and NRPEB-DPS (Part 2) netRAPID Chip Carrier | Design Guide DOC111004DG04EN | Revision 4 | English | 2014-09 | Released | Public © Hilscher, 2013-2014
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Schematics 9.
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Schematics 65/72 Figure 24: Schematic NRPEB-RE2 (Part 2) netRAPID Chip Carrier | Design Guide DOC111004DG04EN | Revision 4 | English | 2014-09 | Released | Public © Hilscher, 2013-2014
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Bill of material 66/72 10 Bill of material 10.1 Overview The following tables contain the parts which are used on the Evaluation Boards. These tables contain the description, type and a manufacturer of the part. 10.2 NRPEB-CCS and NRPEB-DPS Both Evaluation Boards only differ in the field bus connector and the baud rate switch: Evaluation Board NRPEB-CCS has X50 (CC-Link connector) and S0 (baud rate switch), while NRPEB-DPS has X30 (PROFIBUS connector) but no S0 (baud rate switch).
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Bill of material Reference 67/72 Description # Type (manufacturer) Manufacturer S0 S1 S2 Rotary code switch BCD angled, (NRPEB-CCS) SMD 3 COPAL Typ SA-7111TA Copal T1 T2 Push button Tyco 2 FSMSMTR, 1437566-4 Tyco/AMP V1 V11 LED yellow/green SMD 2 629885 HSMF-C166 Avago V12 V13 LED red/green SMD 2 HSMF-C165 Avago V3 Transient Suppressor USB port 1 229011 SN65220DBVT Texas Instruments V104 V105 Schottky Diode SMD 2 PMEG4005AEV,115 PMEG4005AEV,115 NXP (Philips) V106 V107 Tran
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Bill of material 68/72 10.3 NRPEB-RE2 Reference Description # Type (manufacturer) Manufacturer C1 Ceramic capacitor SMD1808 1 1808J2K00222KXT 2.2nF 2KV 10% SMD 1808 X7R Syfer C5 C6 C107 Ceramic capacitor SMD0805 3 35.70.05 10uF 10V SMD0805 X5R 15% Samsung C100 C101 C102 Ceramic capacitor SMD1210 3 UMK325C7106KM-L 10uF 50V X7S SMD 1210 Taiyo Yuden C103 C105 Ceramic capacitor SMD0805 2 31.65.76 100nF 50V SMD 0805 X7R 10% Samsung C104 Ceramic capacitor SMD0603 1 31.17.
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Bill of material 69/72 Reference Description # Type (manufacturer) Manufacturer X11 Foil connector 1 08FLZ-RSM2-TB(LF)(SN) JST X50 RJ45 socket 8-pin 2-ports shielded 2xLED 1 278406 RJHSE-5381-02 Amphenol X100 Power supply chassis socket 1 Lumberg Typ 1613 13 Lumberg Table 49: Bill of material for NRPEB-RE2 netRAPID Chip Carrier | Design Guide DOC111004DG04EN | Revision 4 | English | 2014-09 | Released | Public © Hilscher, 2013-2014
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Appendix 70/72 11 Appendix 11.1 List of tables Table 1: List of revisions...................................................................................................................................................... 4 Table 2: Product overview................................................................................................................................................... 8 Table 3: Interface and standard functions overview ..........................................................
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Appendix 71/72 11.2 List of figures Figure 1: Evaluation Board, 3 pcs. netRAPID and Evaluation DVD with software tools ...................................................... 7 Figure 2: netRAPID tray containing 24 pcs. for series production ....................................................................................... 8 Figure 3: NRP 10-CCS block diagram...............................................................................................................................
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Appendix 72/72 11.3 Contacts Headquarters Germany Hilscher Gesellschaft für Systemautomation mbH Rheinstrasse 15 65795 Hattersheim Phone: +49 (0) 6190 9907-0 Fax: +49 (0) 6190 9907-50 E-Mail: info@hilscher.com Support Phone: +49 (0) 6190 9907-99 E-Mail: de.support@hilscher.com Subsidiaries China Japan Hilscher Systemautomation (Shanghai) Co. Ltd. 200010 Shanghai Phone: +86 (0) 21-6355-5161 E-Mail: info@hilscher.cn Hilscher Japan KK Tokyo, 160-0022 Phone: +81 (0) 3-5362-0521 E-Mail: info@hilscher.