Specifications

LV5692P, LV5693P Application Note

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In using LV5692P/93P, you have to check the following prior to the set design.

1. Absolute Maximum Rating (Common notes to general semiconductor device)

Stresses exceeding Maximum Ratings may damage the device. If stresses exceeding Maximum

Ratings are applied to an IC, it might smoke or fire by the breakdown and the overheating.

We recommend derating design for reducing failure rate of device. A guide of general derating

design is described below.

(1)Stress Voltage: 80% or less for Abs Max voltage.

(2)Maximum rating current: 80% or less for Abs Max Io.

(3)Temperature: 80% or less for Temperatures rating.

2. Recommended Operating Range

When Power Supply IC was used in Recommended Operating Rating and Temperature rating,

IC’s characteristics are guaranteed. Unless otherwise specified, we do not guarantee the specified

value in all temperature ranges. As long as the IC is at operation temperature range, IC’s

characteristic doesn’t change suddenly. Operating conditions of the input voltage and the output

current are limited by the chip maximum junction temperature (Tjmax). Please decide the value of

the input voltage and the output current so as not to exceed Tjmax.

3. Output Capacitor

Between GND and each output, please be sure to put capacitor to prevent oscillation. Because

abrupt changes of input voltage and output load interfere in the output voltage, make sure to use

the system that will actually be offered to the market and define the output capacitor after a

sufficient evaluation. When selecting the capacitor, to ensure the required minimum capacity over

all operating conditions of the application, it is necessary to consider the influence of temperature

and applied voltage on the capacity value.

Please design the PCB layout that the output terminal and the capacitor are located as close as

possible.

4. Parasitic Devices

Output Power MOS-FET driver has, in device structure, parasitic diode like the figure below.

Because in normal operating the input voltage is higher than the output voltage, the parasitic diode

is reverse bias. If the output is higher than the input at abnormal operating, a current flows from the

output to the input, because the parasitic diode is forward biased.

SOURCE(S)

GATE(G)

DRAIN(D)

p－

p＋

Parasitic diode

p＋

GATE(G)

SOURCE(S)

DRAIN(D)

Parasitic diode