Specifications

LV5692P, LV5693P Application Note
http://onsemi.com
22
(Note1) Make sure that the capacitors of the output pins are 10uF or higher and ESR is 10ohm or lower in
total and temperature characteristics and accuracy are taken into consideration. Also the E-cap should have
good high frequency characteristics.
How to set USB application
■USB block diagram
■General description
USB output is controled by CTRL3 pin.
USBGT(PIN10) is gate drive terminal of P-channel FET.
FB(PIN9) is feedback input.
RSNS(PIN12) is current sense input. When voltage difference (VCC-RSNS) exceeds 0.3V, current limits
output current and foldback output voltage.
Limit current is determined by following equation. Io_lim(A)=0.3V/R3(ohm)
■Example parts list
R1,R2
USB voltage setting resistor
R1/R2=9.1kΩ/27kΩ
for 5.0V
Use resistor w/ accuracy better
than ±1%
R3
USB current limit setting resistor
0.1Ω for Ipeak=3A
Panasonic ERJB1CFR10U (ref)
C10
Output voltage stabilizer
0.22uF or higher
(Note1)
Ceramic-cap
C11
Output voltage stabilizer
10uF or higher
(Note1)
E-cap
C12,C13
Phase compensator
C12=1000pF,
C13=0pF
Ceramic-cap
*The purpose of C12 is phase compensation of negative feedback, which guarantees regulator stability.
Recommended value range of C12 is between 470p～2000pF.
If you use the value out of the range, it causes the effect described below.
USB
RSNS
USBGT
FB
C12
C10
Vref
LIM
R3
R2
R1
C11
M1