Specifications

5-7
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A.C. Testing Input, Output Waveform
Test Circuit
Switching Waveforms
FIGURE 6. DATA INPUT CYCLE FIGURE 7. CONTROL REGISTER LOAD
CYCLE
FIGURE 8. STATUS FLAG OUTPUT
ENABLE TIME OR DATA OUT-
PUT ENABLE TIME
TBR1 - TBR8 VALID DATA
TBRL
(4)
t
SET
(2)
t
PW
(5)
t
HOLD
(5)
t
HOLD
(2)
t
PW
(4)
t
SET
VALID DATA
CLS1, CLS2, SBS, PI, EPE
CRL
(6)
t
EN
SFD
RRD
STATUS OR
RBR1 - RBR8
FIGURE 9.
NOTE: A.C. Testing: All input signals must switch between V
IL
- 50% V
IL
and V
IH
+ 20% V
IH
. Input rise and fall times are driven at 1ns/V.
INPUT
V
IH
+ 20% V
IH
V
IL
- 50% V
IL
1.5V 1.5V
OUTPUT
V
OH
V
OL
FIGURE 10.
NOTE: Includes stray and jig capacitance, C
L
= 50pF.
OUT
C
L
(SEE NOTE)
HD-6402