Specifications

5-2
Functional Diagram
Control Definition
CONTROL WORD CHARACTER FORMAT
CLS 2 CLS 1 PI EPE SBS START BIT DATA BITS PARITY BIT STOP BITS
0 0 0 0 0 1 5 ODD 1
0 0 0 0 1 1 5 ODD 1.5
0 0 0 1 0 1 5 EVEN 1
0 0 0 1 1 1 5 EVEN 1.5
0 0 1 X 0 1 5 NONE 1
0 0 1 X 1 1 5 NONE 1.5
0 1 0 0 0 1 6 ODD 1
0 1 0 0 1 1 6 ODD 2
0 1 0 1 0 1 6 EVEN 1
0 1 0 1 1 1 6 EVEN 2
0 1 1 X 0 1 6 NONE 1
0 1 1 x 1 1 6 NONE 2
1 0 0 0 0 1 7 ODD 1
1 0 0 0 1 1 7 ODD 2
1 0 0 1 0 1 7 EVEN 1
1 0 0 1 1 1 7 EVEN 2
1 0 1 X 0 1 7 NONE 1
1 0 1 x 1 1 7 NONE 2
1 1 0 0 0 1 8 ODD 1
1 1 0 0 1 1 8 ODD 2
1 1 0 1 0 1 8 EVEN 1
1 1 0 1 1 1 8 EVEN 2
1 1 1 X 0 1 8 NONE 1
1 1 1 x 1 1 8 NONE 2
(24) TRE
(22) TBRE †
(23)
TBRL
(40) TRC
(38) CLS1
(37) CLS2
(34) CRL
(21) MR
(17) RRC
(18)
DRR
(19) DR †
(16) SFD
† OE † FE † PE
(15)
(14)
(13)
(5) (6) (7)
† RBR8
3-STATE
BUFFERS
(8) (9) (10) (11) (12)
† RBR1
RECEIVER BUFFER REGISTER
RECEIVER REGISTER
MULTIPLEXER
MULTIPLEXER
TRANSMITTER REGISTER
TRANSMITTER BUFFER REGISTER
START
STOP
PARITY
LOGIC
PARITY
LOGIC
START
LOGIC
STOP
LOGIC
CONTROL
REGISTER
RECEIVER
TIMING AND
CONTROL
TRANSMITTER
TIMING AND
CONTROL
† THESE OUTPUTS ARE
THREE-STATE
(4) RRD
(20) RRI
(35) PI
(39) EPE
(16) SFD
(36) SBS
(25) TRO
(26)
TBR1(27)
(30)
(29)
(28)
(31)
(32)
(33)TBR8
HD-6402