Product Info

LTE Module Series
EC21 Hardware Design
EC21_Hardware_Design
3-56
/ 105
The following figure shows a reference design of SGMII interface with PHY AR8033 application.
Figure 29: Reference Circuit of SGMII Interface with PHY AR8033 Application
In order to enhance the reliability and availability in customers’ applications, please follow the criteria
below in the Ethernet PHY circuit design:
 Keep SGMII data and control signals away from other sensitive circuits/signals such as RF circuits,
analog signals, etc., as well as noisy signals such as clock signals, DCDC signals, etc.
 Keep the maximum trace length less than 10-inch and keep skew on the differential pairs less than
20mil.
 The differential impedance of SGMII data trace is 100Ω±10%, and the reference ground of the area
should be complete.
 Make sure the trace spacing between SGMII RX and TX is at least 3 times of the trace width, and the
same to the adjacent signal traces.
Table 24: Pin Definition of USB_BOOT Interface
Pin Name
Pin No.
I/O
Description
Comment
USB_BOOT
115
DI
Force the module enter into
emergency download mode
1.8V power domain.
Active high.
It is recommended to
reserve test point.
The following figure shows a reference circuit of USB_BOOT interface.