Product Info

LTE Module Series
EC21 Hardware Design
EC21_Hardware_Design
3-50
/ 105
SD_INS_DET
23
DI
SD card insertion detection
1.8V power domain.
If unused, keep it open.
The following figure shows a reference design of SD card.
Figure 25: Reference Circuit of SD card
In SD card interface design, in order to ensure good communication performance with SD card, the
following design principles should be complied with:

The voltage range of SD card power supply VDD_3V is 2.7V~3.6V and a sufficient current up to 0.8A
should be provided. As the maximum output current of VDD_SDIO is 50mA which can only be used
for SDIO pull-up resistors, an externally power supply is needed for SD card.

To avoid jitter of bus, resistors R7~R11 are needed to pull up the SDIO to VDD_SDIO. Value of these
resistors is among 10KΩ~100KΩ and the recommended value is 100KΩ. VDD_SDIO should be used
as the pull-up power.

In order to adjust signal quality, it is recommended to add 0Ω resistors R1~R6 in series between the
module and the SD card. The bypass capacitors C1~C6 are reserved and not mounted by default. All
resistors and bypass capacitors should be placed close to the module.

In order to offer good ESD protection, it is recommended to add a TVS diode on SD card pins near
the SD card connector with junction capacitance less than 15pF.

Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DCDC signals, etc.

It is important to route the SDIO signal traces with total grounding. The impedance of SDIO data
trace is 50Ω (±10%).

Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of
SDIO bus should be less than 15pF.

It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm
and the total routing length less than 50mm. The total trace length inside the module is 27mm, so the
exterior total trace length should be less than 23mm.