Product Info

LTE Module Series
EC21 Hardware Design
EC21_Hardware_Design
3-48
/ 105
PCM_SYNC
26
IO
PCM data frame
synchronization signal
1.8V power domain
PCM_CLK
27
IO
PCM data bit clock
1.8V power domain
I2C_SCL
41
OD
I2C serial clock
Require external pull-up to 1.8V
I2C_SDA
42
OD
I2C serial data
Require external pull-up to 1.8V
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048KHz PCM_CLK and 8KHz PCM_SYNC. Please refer to
document [2] about AT+QDAI command for details.
The following figure shows a reference design of PCM interface with external codec IC.
Figure 24: Reference Circuit of PCM Application with Audio Codec
1. “*” means under development.
2. It is recommended to reserve RC (R=22Ω, C=22pF) circuits on the PCM lines, especially for
PCM_CLK.
3. EC21 works as a master device pertaining to I2C interface.
3.12. SD Card Interface
EC21 supports SDIO3.0 interface for SD card.
The following table shows the pin definition of SD card interface.
NOTES