Product Info

LTE Module Series
EC21 Hardware Design
EC21_Hardware_Design
3-34
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To decrease voltage drop, a bypass capacitor of about 100µF with low ESR (ESR=0.7Ω) should be used,
and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low ESR. It
is recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing the MLCC array,
and place these capacitors close to VBAT_BB/VBAT_RF pins. The main power supply from an external
application has to be a single voltage source and can be expanded to two sub paths with star structure.
The width of VBAT_BB trace should be no less than 1mm; and the width of VBAT_RF trace should be no
less than 2mm. In principle, the longer the VBAT trace is, the wider it will be.
In addition, in order to get a stable power source, it is suggested that a zener diode whose reverse zener
voltage is 5.1V and dissipation power is more than 0.5W should be used. The following figure shows the
star structure of the power supply.
Figure 8: Star Structure of the Power Supply
3.5.3. Reference Design for Power Supply
Power design for the module is very important, as the performance of the module largely depends on the
power source. The power supply should be able to provide sufficient current up to 2A at least. If the
voltage drop between the input and output is not too high, it is suggested that an LDO should be used to
supply power for the module. If there is a big voltage difference between the input source and the desired
output (VBAT), a buck converter is preferred to be used as the power supply.
The following figure shows a reference design for +5V input power source. The typical output of the power
supply is about 3.8V and the maximum load current is 3A.