Specifications

Section 4. Sensor Support
4-9
FIGURE 4.2-1. Full and ½ Cycle Integration Methods for
AC Power Line Noise Rejection
4.2.5.1.2 AC Noise Rejection on Large Analog Signals
W
hen rejecting AC noise on the 2500 mV and 5000 mV ranges, the CR1000
makes two fast measurements separated in time by ½ line cycle, as illustrated
in FIGURE 4.2-1. For 60 Hz rejection , ½ line cycle = 8333 μs, m
eaning that
the 2
nd
measurement must start 8333 μs after the integration for the first
measurement was started. The A/D conversion time is approximately 170 μs,
leaving a maximum input settling time of approximately 8333 μs - 170 μs =
8160 μs before the 2
nd
measurement is delayed too long to result in a rejection
notch at 60 Hz. For 50 Hz rejection on the mV5000 and mV2500 input ranges,
the maximum input settling time of approximately 10,000 - 170 μs = 9830 μs
before the 2
nd
measurement is delayed too long to result in a rejection notch at
50 Hz. The CR1000 does not prevent or warn against setting the settling time
beyond the ½ cycle limit. TABLE 4.2-6 lists details of the ½ line cycle AC
p
ower line noise rejection technique.