Product Manual

Table Of Contents

Cambricon®

Frequency -- 100 156.25 400 MHz

Frequency offset -- -100 -- 100 PPM

Maximum voltage value -- -- -- 3.3 V

Minimum voltage value -- GND -- -- V

Differential swing -- 0.15 -- 1.3 V

Duty cycle -- 45 50 55 %

Phase noise jitter 12KHz –20MHz -- -- 270 fs RMS

4.3.2 PCIE signal

MLU290-M5 Intelligent Accelerating Card supports PCIE GEN4.0 x16 bit width default.There is no

AC coupling capacitor in MLU290-M5. Sending and receiving AC coupling capacitors are placed on the

baseboard and the value range is 176nF-265nF (220nF recommended). The placement position

reference diagram is as follows:

Mirror Mezz

connector

MLU290

CPU/Switch

MezzCradBaseBorad

220nF

4Figure 4.4 PCIE AC Coupled Capacitance

PE_REFCLK reference clock shall meet the requirements of PCIE GEN4.0 specification, phase noise

jitter should be less than 0.5 ps.

6Table 4.6 PE_REFCLK Specifications

Signal

Direction of signal

Signal description

PETp/n [15:0] O

PCIE sending signal. MLU290-M5 send,

baseboard receive.

PERp/n [15:0] I

PCIE receiving signal. MLU290-M5 receive,

baseboard send.