Product Manual

Cambricon®
Copyright © 2020 Cambricon Corporation
11
54VDC In
Fuse
20 Amp
Littlfuse 456
Hot Swap
Mosfet
Hot Swap
Ckt
MezzCard
0.1uF
TVS
47uF
Qty=6
10uF
Qty=10
GND
GND
2Figure 4.2 HSC block diagram
LM5069 and LM5066I of TI are recommended by the HSC controller.The selection of MOS should
focus on SOA curve. Infineon IPB017N10N5LF and Nexperia PSMN4R8-100BSE are recommended.
4.2.4 Power on time sequence
When MLU290-M5 Intelligent Accelerating Card power on normally with DC 54V voltage,the
HOST_PWRGD signal is sent out after the reference clock (156.25MHz) is stable.Detailed timing
sequence is as follows:
54V
HOST_PWRGD
AUX_156M_REFCLK
<4s
>100ms
3Figure 4.3 Power on Timing Sequence
4.3 Signal description
4.3.1 Clock signal
AUX_156M_REFCLKp/n receiving support LVPECL,LVDS,CML,HCSL and other common differential
level signal input.As a CCLINK high-speed SERDES reference clock, its phase noise jitter is required less
than 270fs.
5 Table 4.5 AUX_156M_REFCLK Specifications
Parameters
Conditions
Minimum
value
Typical
values
Maximum
value
Units