LTE RRH B40/B41 Quick Guide Cambium Networks 2GHz Palisade 220 V1.0 Wuhan Gewei Electronic Technologies Co. Ltd. Wuhan Gewei Electronic Technologies Co. Ltd.
Content 1 STRUCTURE &INTERFACE DESCRIPTION .......................................................................... 1 1.1 STRUCTURE &FRONT INTERFACE ............................................................................................. 1 1.1.1 Front Interface Description ............................................................................................. 2 1.1.2 Power Interface ...............................................................................................................
1 Structure &Interface Description 1.1 Structure &Front Interface The LTE RRH B40/B41 structure &interface is shown as Figure 1-1: Figure 1-1 st ruct ure of LTE RRH B40/B41 Figure 1-2 LTE RRH B40/B41 front int erface Wuhan Gewei Electronic Technologies Co. Ltd.
1.1.1 Front Interface Description Table 1-1 LTE RRH B40/B41 Front Interface Description # External interface description Remarks 1 Chassis ground 2 POWER -48V DC Power supply Interface. Please refer to 1.1.2 for Pin definition 3 VENT Air vent 4 OPT Optical interface 5 ANT0 N connector. Actually Antenna port 2(ANT2) This will be modified in next version 6 ANT1 N connector. 1.1.
C Negative -48V 1.2 Side Interface LTE RRH B40/B41 side interface is shown in Figure 1-3; Figure 1-4 LTE RRH B40/B41 Side Interface 1.2.1 Side Interface Description Table 1-3 LTE RRH B40/B41 Side Interface Description # Description 1 2 3 4 5 6 Reserve Reserve Reserve Reserve Reserve Reserve Wuhan Gewei Electronic Technologies Co. Ltd.
1.2.2 Service Access and Operation Maintenance Window The service access and operation maintenance window is mainly used for service access, debug and maintenance for LTE RRH B40/B41. The window is closed by default when the product is fresh out of factory, a screwdriver is needed to open the window when needed, the window view is as shown in Figure 1-5.
2 Hardware testing connection 2.1 Hardware Required Equipment # Item Name Qty 1 Optical Transceiver 1 2 Fiber 1 3 Debug Cable 1 4 DC Power source 1 5 Power Supply Cable 1 6 PC 1 7 High Power Attenuator 8 BBU 1 9 UE 1 10 LTE RRH B40/B41 1 11 RF Cable Several Remark link rate should up to 4.9125Gb/s See Appendix A More than 10W Several 2.2 Software preparation PuTTY PuTTY software is free and open source, supports serial port and telnet debugging.
2.3 Serial and Ethernet Configuration Serial： 115200, 8N1, No Flow control Ethernet: The default IP is blow IP : 192.168.114.200 setting putty as below: Item Mode Software Description Remark The COM may be different 1 UART PuTTY when choosing different port in PC. ◆The “Serial line to connect to” should indicate the actual serial port used on your PC for debugging. ◆ Please set the Speed (baud) parameter to 115200 since the LTE RRH B40/B41 baud rate is 115200.
2.4 Connection figure RF Cable ATT: ~35dB RF Cable ATT: ~35dB UE RF Cable RF Cable Z2R-L1 BBU Optical Cable -48V DC PC UART Debug Cable ETH PSU 1.the output power of LTE RRH B40/B41 will be 2W per antenna when -15dBFS digital signal input from CPRI, so please choose proper Attenuator to protect UE. 2. the Debug Cable is compose of UART and eth, the detail information this cable is Appendix A.
3 Hardware Test list Test Item # Test Point Description Typ 1. TP1 Output of regulator U2（NCP3231） 1.020～0.920V 2. TP2 Output of regulator U3（TPS54620） 2.040～1.960V 3. TP4 Output of regulator U5（TPS54620） 3.570～3.430V 4. TP3 Output of regulator U6（NCP3231） 1.530～1.470V 5. TP5 Output of regulator U7(TPS74801) 1.267～1.332V 6. TP7 Output of regulator U9(TPS74801) 1.267～1.332V 7. TP8 Output of regulator U10(ISL80101) 4.850～5.150V 8. TP9 Output of regulator U11(NCP59744) 1.
Appendix A The information of debug port 1.The debug port location The block diagram describe the general location of the debug port in our board JTAG Connector 1 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FPGA_TMS FPGA_TCK FPGA_TDO FPGA XC7Z035 FPGA_TDI PS_SRST_B The First Debug Port GEPHY board Transformer 7 6 5 4 3 2 ETH_TX_P 8 ETH_TX_N RS232_DBG_TXD ETH_RX_P ETH_RX_N RS232_DBG_RXD RS232 Debug Port 1 Connector RJ45 2 The Second Debug Port 2.
