Specifications

26 Motorola 56F8300 Hybrid Controller Family Motorola
The Pace-Setting Performance and Features of the 56F8300 Hybrid Controllers
Figure 1-15. ADC Delay Triggering Mechanism
The ADC also has unique capabilities to process and extract information from ADC samples. Level
and threshold detection are shown in Figure 1-16. The ADC can perform limit checking and zero
crossing detection with no CPU intervention. Each ADC channel has its own upper, lower, and
threshold comparators, allowing for completely independent channel operation and levels.
Figure 1-16. ADC Limit and Threshold Crossing
The ADC module has an internal self-calibration capability. Internal to the ADC is a highly accurate
voltage reference system that can feed stable known voltages into any ADC input, allowing for
software to read the conversion and adjust for any residual gain and offset errors.
The ADC also has a sophisticated set of power-down modes that still let normal conversions occur.
The ADC can automatically power itself down between conversions and wake itself back up when a
trigger event occurs.
ADC convert signal
from Sync Module
Control
Algorithm
Execution
PWM values applied to plant
T
delay
T
delay
Interrupt
Latency
ADC
Convert
Interrupt from
Sync Module
Events can be pipelined
Phase Margin is increased
Closed loop stability is enhanced
The closer this resembles an
impulse function, the better!
Digital Conversion Result
Programmable Upper Limit
Programmable Lower Limit
Programmable Threshold
Optional Interrupts
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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