Specifications

The Pace-Setting Performance and Features of the 56F8300 Hybrid Controllers
MOTOROLA Motorola 56F8300 Hybrid Controller Family 21
• Capable of multiple motor control
— 60 MIPS hybrid controller allows execution of multiple tasks
— Separate PWM pulse width register for each PWM channel
— Separate fault signal input for each PWM pair
— Separate current status input for each PWM pair
Figure 1-9 illustrates a partial functional block of the PWM module.
Figure 1-9. PWM Module Functional Block Diagram
The following sections offer examples using PWM features. Figure 1-10 shows configuration of the
PWM fault inputs to selectively disable a PWM complementary channel, then automatically clears the
fault on the next PWM cycle. The fault generation and clearing occurs without software intervention,
but the software can be notified of the event with the generation of an interrupt. This demonstrates how
the PWM can be used in a safe but fault-tolerant mode.
Prescaler
PWM
Counter
Comparator
#1
PWM Value
Register #1
Comparator
#0
PWM Value
Register #0
Dead Time Generation
OUT1
OUT0
OUTCTR0
(Software Ctr)
Channel
Swap
Independent
Mode
IPBUS
Clock
Fault Decoder
& Fault
AND
AND
XOR
XOR
Fault0
Fault1
Fault2
Fault3
MASK0
MASK1
XOR
XOR
Polarity
Control
Polarity
Control
PWM0
PWM1
Output
Pad
Enable
Q D
CLK
PWM Value
Register Select
PWM Cycle
Start
Prescaler
PWM
Counter
Comparator
#1
PWM Value
Register #1
Comparator
#0
PWM Value
Register #0
Dead Time Generation
OUT1
OUT0
OUTCTR0
(Software Ctr)
Channel
Swap
Independent
Mode
IPBUS
Clock
Fault Decoder
& Fault
AND
AND
XOR
XOR
Fault0
Fault1
Fault2
Fault3
MASK0
MASK1
XOR
XOR
Polarity
Control
Polarity
Control
PWM0
PWM1
Output
Pad
Enable
Q D
CLK
PWM Value
Register Select
PWM Cycle
Start
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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