Specifications

The Pace-Setting Performance and Features of the 56F8300 Hybrid Controllers
MOTOROLA Motorola 56F8300 Hybrid Controller Family 15
The 56F8300 devices’ advanced architecture is the successful merger of several types of processors.
When Motorola created the 56800E core, it challenged its world-class core designers to create a core
incorporating the best points of its 8-bit, 16-bit, and 32-bit MCU cores with the performance of its
digital signal processing cores. The designers succeeded with the 56800E. The 56F8300 devices merge
the 56800E core with Motorola’s best-in-class Flash memory technology and the exceptional level of
integration customers have come to expect from the number one supplier of embedded processors. The
result is a 56F8300 Series that offers:
• Signal processing power of a DSP
• Ease of programming of a 16-bit MCU
• 32-bit performance with 16-bit code density
3.2 Internal Peripherals
3.2.1 External Memory Interface (EMI)
The EMI peripheral connects directly into the core buses for optimum performance. This
high-performance peripheral enables a glueless connection to external memory and peripherals.
Figure 1-7 shows the EMI’s block diagram.
Figure 1-7. EMI Block Diagram
XAB1[23:0]
CBW[31:0]
CDBR_M[31:0]
PRIMARY DATA ACCESS
SECONDARY DATA READ
XAB2[23:0]
XDB2_M[15:0]
PROGRAM MEMORY ACCESS
PAB[20:0]
CDBW[15:0]
PDB_M[31:0]
XAB1[23:0]
CDBW[31:0]
CDBR_M[31:0]
XAB2[23:0]
XDB2_M[15:0]
PAB[20:0]
PDB_M[31:0]
C7WAITST
HOLDOFF
CLK
A[23:0]
D[15:0]
CS
[7:0]
RD
WR
FLASH_SECURITY_EN
EMI
56800E CORE
CLOCK
GEN.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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