Specifications

14 Motorola 56F8300 Hybrid Controller Family Motorola

The Pace-Setting Performance and Features of the 56F8300 Hybrid Controllers

The 56800E core has a very powerful bus structure that maximizes the performance of the internal

memory. Table 3 shows the types of memory in the 56F8300 and how each can be used. The Program

Flash, RAM, and BootFlash areas are flexible and can store program code or data. The BootFlash is a

separate Flash block that comes from the factory programmed with a standard Boot Loader. The

BootFlash can be used as program or data space if a special Boot Loader is not required in the

application. By making the boot memory Flash-based, the 56F8300 gives the customer the flexibility

to replace the standard Boot Loader with his own custom implementation. And since the BootFlash is

a separate block of memory, there is an extra level of protection, so that even if power is lost while

reprogramming the Program Flash, the device will still boot correctly when power is restored.

The Data Flash and RAM are very flexible and support native 8-bit, 16-bit, or 32-bit types. This means

that 8-bit data types, such as a “char” in C, can be very effectively packed and manipulated in memory.

But at the same time, 32-bit data types can be moved in a single cycle via the internal 32-bit data buses

present in the entire line of 56800E processors.

The 56800E internal bus structure is a modified Harvard architecture with seven internal program and

data buses, two of them 32 bits wide. The internal data RAM is dual-ported, so it supports dual

accesses in a single cycle. The Data Flash can also be accessed at the same time as the Data RAM. This

enables both single- and dual-parallel reads, as well as a program fetch on a single cycle; coupled with

the interruptible no-overhead hardware do loops, it gives 56F8300 devices the greatest signal

processing performance when operating from Flash.

The number, width, and flexibility of the internal bus structure and how they are connected to the

internal memories can be critical in determining how well a processor can zoom through signal

processing chores and can efficiently service interrupt-intensive control applications. Serious

performance bottlenecks can occur in the absence of the right instructions in the core, the correct bus

structure, and the proper memory interface. These bottlenecks can cause performance to be up to six

times slower in signal processing than in a 56F8300 device. An advanced hybrid architecture must

support the proper number and width of buses to perform true dual-parallel reads and requires an

interruptible, zero-overhead do loop support in the instruction set to be able to properly perform the

signal processing functions.

The 56F8300 performance is easy to understand: Real 60MHz Flash operation over the entire

operational temperature range, with the right structure, number, and width of internal buses to perform

control-oriented signal processing without bottlenecks.

Table 3: Memory Configuration

Type Features

Program Flash Program/Data, 16-bit

Program RAM Program/Data, 16-bit

Data Flash Data, 8/16/32-bit

Data RAM Data, 8/16/32-bit

BootFlash Program/Data, 16-bit

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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