User Manual

CIRCUIT DESCRIPTION
4-5
June 1997
Part No. 001-3412-002
When J201, pin 4 is high in receive (+3-16V),
Q173 is turned on and the collector voltage goes low.
A low on the base of Q172 turns the transistor on and
the regulated +9.6V on the emitter is on the collector
for the receive circuitry. Q171 applies a low on the
base of Q841, the transistor is off and the collector is
high. With a high on the base of Q842 and a low on
the emitter, this reverse biases CR850 for a high
impedance.
The capacitive leg on the VCO board is formed
by C851, CR850, C852 and C876. When J201, pin 4
is low in transmit, Q842 is turned on and a high is on
the emitter, Q171 is turned off and the collector volt-
age goes high. A low on the base of Q173 turns the
transistor off and the regulated +9.6V is removed from
the receive circuitry. With a high on the base of Q841
the transistor is on and the collector is low. With a
low on the collector of Q842 and a high on the emit-
ter, this forward biases CR850 and provides an RF
ground through C851 and C852/C876 are effectively
connected to the tank circuit. This decreases the reso-
nant frequency of the tank circuit.
4.2.7 SYNTHESIZER IC (U811)
Introduction
Synthesizer chip U811 is shown in Figure 4-2.
This device contains the following circuits: R (refer-
ence), Fractional-N, NM1 and NM2; phase and lock
detectors, prescaler and counter programming
circuitry. The basic operation was described in
Section 4.2.1.
Channel Programming
Frequencies are selected by programming the R,
Fractional-N, NM1 and NM2 in U811 to divide by a
certain number. These counters are programmed by
Loader board or a user supplied programming circuit.
More information on programming is located in
Section 3.
As previously stated, the counter divide numbers
are chosen so that when the VCO is oscillating on the
correct frequency, the VCO-derived input to the phase
detector is the same frequency as the reference oscilla-
tor-derived frequency.
The VCO frequency is divided by the internal
prescaler and the main divider to produce the input to
the phase detector.
4.2.8 LOCK DETECT
When the synthesizer is locked on frequency, the
SYNTH LOCK output of U811, pin 18 (J201, pin 7) is
a high voltage. When the synthesizer is unlocked, the
output is a low voltage. Lock is defined as a phase
difference of less than 1 cycle of the TCXO.
4.3 RECEIVER CIRCUIT DESCRIPTION
4.3.1 HELICAL FILTER (Z201), RF AMPLIFIER
(Q201)
Capacitor C205 couples the receive signal from
the antenna switch to helical filter Z201. (The antenna
switch is described in Section 4.4.4.) Z201 is a band-
pass filter tuned to pass only a narrow band of fre-
quencies to the receiver. This attenuates the image
and other unwanted frequencies. The helicals are fac-
tory set and should not be tuned.
Impedance matching between the helical filter
and RF amplifier Q202 is provided by C206, C207
and L201. CR231 protects the base-emitter junction of
Q202 from excessive negative voltages that may occur
during high signal conditions. Q201 is a switched
constant current source which provides a base bias for
Q202. Q201 base bias is provided by R202/R203.
Current flows through R201 so that the voltage across
it equals the voltage across R202 (minus the base/
emitter drop of Q201). In the transmit mode the
receive +9.6V is removed and Q201 is off. This
removes the bias from Q202 and disables the RF
amplifier in transmit mode. This prevents noise and
RF from being amplified by Q202 and fed back on the
first injection line.
Additional filtering of the receive signal is pro-
vided by Z202. L202, C208 and C209 provide imped-
ance matching between Q202 and Z202. Resistor
R205 is used to lower the Q of L202 to make it less
frequency selective.