User Guide

Chapter 8 Preparing Your Design for Simulation

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For Release 9.2, markers can now be placed on subcircuit

nodes as well. This allows you to perform cross-probing

between Schematics and PSpice at the lower level circuits

of a hierarchical design.

Note If conditional constructs are used, the hierarchical netlist will create

a unique subcircuit definition for each instance.

Creating the netlist

You can generate a flat or hierarchical simulation netlist

(.NET) by using the Create Netlist command from the

Analysis menu. Or, you can create an LVS netlist (.LVS) by

using the Create LVS Netlist from the Tools menu.

During the netlist process, Schematics creates several files

with different extensions: the .NET file contains the

netlist; the .CIR file contains simulation commands; and

the .ALS file contains alias information.

Creating a flat netlist

To create a flat netlist

1 In Schematics, from the Analysis menu, choose Create

Netlist.

Note By default, the Netlist Format will be set to create a flat netlist. If

you have changed the format setting previously in the Netlist

Setting dialog box, the last setting you selected (either flat or

hierarchical) will be saved with the schematic and continue to apply

to that design until you change it again.

Creating a hierarchical netlist

To create a hierarchical netlist

1 From the Options menu, choose Netlist Setting.

The Netlist Setting dialog box appears.

2 Under the Netlist Format frame, click the Hierarchical

radio button to enable it.