User Guide

Chapter 8 Preparing Your Design for Simulation
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Setting Up Analyses
Refer to your PSpice users guide for information about
setting up and running the many different analysis types
supported by PSpice A/D.
Creating a Simulation Netlist
Overview
A netlist is the connectivity description of a circuit,
showing all of the components, their interconnections,
and their values. When you create a simulation netlist
from Schematics, that netlist describes the current design.
For Release 9.2, you now have a choice between two types
of netlist formats:
a flat netlist
a hierarchical netlist
The flat netlist is generated for all levels of hierarchy,
starting from the top, regardless of whether you are
pushed into any level of the hierarchy. Flat netlists are
most commonly used as input to PCB layout tools. The flat
simulation netlist format for PSpice contains device
entries for all parts on a subcircuit (child) schematic
multiple times, once for each instance of the hierarchical
part or block used.
The hierarchical netlist preserves the hierarchical
information in any subcircuit (child) schematics. It
contains a single .SUBCKT definition for each child
schematic. The devices in the subcircuit are therefore
netlisted only once. Each instance of the hierarchical part
or block is then netlisted as an instance of that subcircuit
(as an X device). The subcircuit name corresponds to the
name of the subcircuit (child) schematic.