User Guide

Chapter 4 Creating and Editing Designs

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2 Click the wire segment that you want to change.

3 Click to place a vertex.

4 Double-click to place the last vertex and stop rewiring.

Drawing and Labeling Buses

The connectivity of buses and bus segments in PSpice

Schematics is controlled by labeling. The rules of

connectivity are:

• A bus label specifies the signals it carries and the order

of the signals.

• A bus can connect to another bus only if one is a subset

of the other (such as A[0-31] and A[16-31]).

• A bus electrically connects to a pin of a part or port if

the pin name indicates the same number of signals.

Connection is in the order specified; for example, a bus

labeled A[31-0] connected to a port labeled

Addr[32-63] will electrically connect A[31] with

Addr[32], A[30], with Addr[33], and so on.

• For a wire to be connected to a bus, the wire must be

labeled with one of the signals on the bus.

• Valid syntax for labeling a bus is:

CLK[0-15]

CLK[0:15]

CLK[0..15]

CLK[0-3, 12-15]

CLK1, CLK2, data1, data2, input,...

In the latter form, each and every signal in the bus

must be included in the series. The signals are

separated by commas.

Note Buses must