Manual

220 Series Commercial Grade CF Product Manual v2.0Cactus Technologies

These registers return the status when read by the host. Reading the Status register does clear

a pending interrupt while reading the Auxiliary Status register does not. The meaning of the

status bits are described as follows:

This register is used to control the card interrupt request and to issue an ATA soft reset to the

card. The bits are dened as follows:

4.5.9. Status and Alternate Status Registers

(Address 1F7[177] and 3F6[376]; Osets 7 and Eh)

4.5.10. Device Control Register

(Address—3F6[376]; Oset Eh)

D7 D6 D5 D4 D3 D2 D1 D0

BUSY RDY DWF DSC DRQ CORR 0 ERR

Bit 7 (BUSY) The busy bit is set when the Industrial ATA product has access to the command

buer and registers and the host is locked out from accessing the command

Bit 6 (RDY) RDY indicates whether the device is capable of performing operations requested by

the host. This bit is cleared at power up and remains cleared until the Industrial ATA

product is ready to accept a command.

Bit 5 (DWF) This bit, if set, indicates a write fault has occurred.

Bit 4 (DSC) This bit is set when the Industrial ATA product is ready.

Bit 3 (DRQ) The Data Request is set when the Industrial ATA product requires that information

be transferred either to or from the host through the Data register.

Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the

data has been corrected. This condition does not terminate a multi-sector read

operation.

Bit 1 (IDX) This bit is always set to 0.

Bit 0 (ERR) This bit is set when the previous command has ended in some type of error. The

bits in the Error register contain additional information describing the error.

Bit 7 This bit is an X (Do not care).

Bit 6 This bit is an X (Do not care).

Bit 5 This bit is an X (Do not care).

Bit 4 This bit is an X (Do not care).

Bit 3 This bit is ignored by the card.

D7 D6 D5 D4 D3 D2 D1 D0

X X X X 1 SW Rst -IEn 0